A Fully Integrated Analog Front End for Biopotential Signal Sensing

Zheng, Jiawei; Ki, Wing-Hung; Tsui, Chi-Ying

doi:10.1109/tcsi.2018.2854741

Cited by 38 publications

(5 citation statements)

References 24 publications

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“…L OW frequency filters are key building blocks in biosignal detection systems, earthquake prediction systems, structure health monitoring and stabilization control circuits, where the frequencies of interest typically range from DC to a few tens of kHz [1][2][3]. In order to achieve such low cut-off frequencies, large capacitors and/or large resistors are required, which are impractical in fully integrated solutions.…”

Section: Introductionmentioning

confidence: 99%

High-Linearity Tunable Low-Gₘ Transconductor Based on Bootstrapping

Cinco-Izquierdo

Blas

Sanz-Pascual

2022

IEEE Trans. Circuits Syst. II

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In this brief, a novel pseudo-differential lowtransconductance amplifier is proposed based on the bootstrapping technique. The transconductor is implemented using two voltage follower topologies as amplifiers with their outputs connected to both terminals of a resistor, thus bootstrapping the voltages at these terminals to increase the equivalent resistance value, and achieve a very low transconductance without the need for large passive components. In this way, a highly-linear compact structure is designed whose transconductance can be tuned by external current sources. The circuit was fabricated in a standard 0.18µm CMOS process. The experimental results show a tunable transconductance in the range of tens of nA/V , with a total harmonic distortion lower than −40dB at 350mV pp@1kHz. The power consumption of the amplifier is 4µW under a 1.8V supply voltage.

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Section: Introductionmentioning

confidence: 99%

High-Linearity Tunable Low-Gₘ Transconductor Based on Bootstrapping

Cinco-Izquierdo

Blas

Sanz-Pascual

2022

IEEE Trans. Circuits Syst. II

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“…Different researchers have focused on different features in their design. For example, some studies have focused on the low power of the amplifier [11,12], some have pursued low noise [13,14,15], while others have paid more attention to the NEF [16,17,18,19], high input impedance [20,21], little distortion [22,23,24] and small area [25,26]. A tradeoff exists between power, noise and area and balancing these performances in design is important.…”

Section: Discussionmentioning

confidence: 99%

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Ni¹,

Han²,

Lei³

et al. 2020

Preprint

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Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.

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“…ADCs that are most commonly used for the ECG signal acquisition are Successive Approximation Register (SAR) and oversampled ADCs. SAR ADCs have moderate accuracy and excellent power to performance ratio, but low resolution of 8 to 12 bits [9,10]. Higher resolution SAR ADCs need high resolution feedback DACs, resulting in increased area and power consumption.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Kavitha

Akhila²,

Kannan

2023

Eng. Technol. Appl. Sci. Res.

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The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

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A Fully Integrated Analog Front End for Biopotential Signal Sensing

Cited by 38 publications

References 24 publications

High-Linearity Tunable Low-Gₘ Transconductor Based on Bootstrapping

High-Linearity Tunable Low-Gₘ Transconductor Based on Bootstrapping

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

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