A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines

Oku, Daisuke; Terada, Kotaro; Hayashi, Masato; Yamaoka, Masanao; Tanaka, Shu; Togawa, Nozomu

doi:10.1587/transinf.2018edp7411

Cited by 25 publications

(9 citation statements)

References 22 publications

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“…We have to embed the Hamiltonian into a suitable topology. In this embedding, the Hamiltonian with n variables theoretically requires n 2 + n Ising spins [9]. Therefore, the cloud environment of CMOS can theoretically handle fully-connected Hamiltonians with up to 319 variables.…”

Section: The Current Annealing Computersmentioning

confidence: 99%

Annealing-Based Algorithm for Solving CVP and SVP

Yamaguchi

Shimizu

Furukawa

et al. 2022

JORSJ

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Inspired by quantum annealing, digital annealing computers specified for annealing computations have been realized on a large scale, such as the Digital Annealer (DA) developed by Fujitsu and the CMOS Annealing Machine developed by Hitachi. With the progress achieved using these computers, it has become necessary to estimate the computational hardness of cryptographic problems. This paper focuses on lattice problems, such as the closest vector problem (CVP) and shortest vector problem (SVP), which are a class of optimization problems. These problems form the basis of the security of lattice-based cryptography, which is a prime candidate for the NIST post-quantum cryptography standardization. For these lattice problems, we propose methods for generating an Ising model and solving the Ising model on annealing computers with a bit representation as the input, which represents encodings to map each integer variable in the SVP into binary variables. We propose two methods for SVPs, a basic method and a variant incorporating approximately the concept of the classical lattice enumeration. In our experimental results obtained using the second-generation DA, we succeeded in finding a shortest nonzero lattice vector in 40-and 45-dimensional lattices in the Darmstadt SVP Challenge. The basic method with a hybrid bit representation was the fastest among our methods with a bit representation, and the expected running time was estimated as 664 and 13,750 seconds for the 40-and 45-dimensional lattices, respectively. These results provide a benchmark for solving the SVP with annealing computers. * This research was conducted when the author was affiliated with Fujitsu.

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Section: The Current Annealing Computersmentioning

confidence: 99%

Annealing-Based Algorithm for Solving CVP and SVP

Yamaguchi

Shimizu

Furukawa

et al. 2022

JORSJ

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“…Current quantum annealing platforms have various physical topologies, chimera graphs for D-waves, and three-dimensional lattices for CMOS annealers [25]. Thus, we need to embed the logical Ising model to a specific graph topology to run the annealing process.…”

Section: Formal Definitionmentioning

confidence: 99%

Petri Net Modeling for Ising Model Formulation in Quantum Annealing

2021

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Quantum annealing is an emerging new platform for combinatorial optimization, requiring an Ising model formulation for optimization problems. The formulation can be an essential obstacle to the permeation of this innovation into broad areas of everyday life. Our research is aimed at the proposal of a Petri net modeling approach for an Ising model formulation. Although the proposed method requires users to model their optimization problems with Petri nets, this process can be carried out in a relatively straightforward manner if we know the target problem and the simple Petri net modeling rules. With our method, the constraints and objective functions in the target optimization problems are represented as fundamental characteristics of Petri net models, extracted systematically from Petri net models, and then converted into binary quadratic nets, equivalent to Ising models. The proposed method can drastically reduce the difficulty of the Ising model formulation.

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“…This type of ME is often called clique ME or completegraph ME because the logical Ising model with all-to-all coupling can be embedded. The algorithms for this type of ME have been developed for D-Wave [25]- [27] and CMOS annealing machines [28]. In the second type, each chain has a different number of spins.…”

Section: A Motivationmentioning

confidence: 99%

Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

2020

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We propose a novel type of minor-embedding (ME) in simulated-annealing-based Ising machines. The Ising machines can solve combinatorial optimization problems. Many combinatorial optimization problems are mapped to find the ground (lowest-energy) state of the logical Ising model. When connectivity is restricted on Ising machines, ME is required for mapping from the logical Ising model to a physical Ising model, which corresponds to a specific Ising machine. Herein we discuss the guiding principle of ME design to achieve a high performance in Ising machines. We derive the proposed ME based on a theoretical argument of statistical mechanics. The performance of the proposed ME is compared with two existing types of MEs for different benchmarking problems. Simulated annealing shows that the proposed ME outperforms existing MEs for all benchmarking problems, especially when the distribution of the degree in a logical Ising model has a large standard deviation. This study validates the guiding principle of using statistical mechanics for ME to realize fast and high-precision solvers for combinatorial optimization problems.

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A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines

Cited by 25 publications

References 22 publications

Annealing-Based Algorithm for Solving CVP and SVP

Annealing-Based Algorithm for Solving CVP and SVP

Petri Net Modeling for Ising Model Formulation in Quantum Annealing

Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

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