A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Upadhyaya, Parag; Poon, Chi Fung; Lim, Siok Wei; Cho, Junho; Roldan, Arianne; Zhang, Wenfeng; Namkoong, Jin; Pham, Thanh-Hang; Xu, Bruce; Lin, Winson; Zhang, Hongtao; Narang, Nakul; Tan, Kee Hian; Zhang, Geoff G. Z.; Frans, Yohan; Chang, Ken

doi:10.1109/isscc.2018.8310207

Cited by 57 publications

(7 citation statements)

References 4 publications

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry ( Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ). With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

Section: Interconnectmentioning

confidence: 99%

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Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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Section: Interconnectmentioning

confidence: 99%

Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

View full text Add to dashboard Cite

show abstract

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry [133]- [142]. With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

Section: A Trend Survey and Challengesmentioning

confidence: 99%

Peer Review #2 of "Today’s computing challenges: opportunities for computer hardware design (v0.2)"

2021

View full text Add to dashboard Cite

Due to explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing limit, and therefore they are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a big challenge for computer hardware industry. However, at the same time it also provides great opportunities to hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today's computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…When estimating the probability of a codeword containing 100 FEC symbol errors, the relative estimation error is bounded by the worst-case scenario having 100 consecutive errors, 1-(1-0.0001) 100 ≈ 1%. As modern SerDes links generally operate with a pre-FEC BER ≤ 10 −2 , m = 10, N ≤ 4, t = 15 100, and α ≤ 0.4 [19]- [21], the simplified trellis model can be practically applied to the post-FEC error-rate analysis with an estimation error much less than 1%. In addition, we can always apply the original 4 N -state PAM trellis to verify the results generated by the simplified model.…”

Section: -Pam Trellis Model Simplificationmentioning

confidence: 99%

“…A Markov chain model from [17] was adopted in [16] to account for DFE error propagation, and possible burst-error patterns are systematically grouped through trellis-based dynamic programming. However, 4-PAM signaling is becoming increasingly critical for 50 Gb/s+ wireline links [18]- [20], often with DFEs [21], [22]. Hence more powerful Reed-Solomon (RS) codes are being used to correct up to t FEC symbol errors caused by DFE error propagation.…”

mentioning

confidence: 99%

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation

Yang

Shahramian

Shakiba

et al. 2020

IEEE Trans. Circuits Syst. I

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This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10 −15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.

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A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Cited by 57 publications

References 4 publications

Today’s computing challenges: opportunities for computer hardware design

Today’s computing challenges: opportunities for computer hardware design

Peer Review #2 of "Today’s computing challenges: opportunities for computer hardware design (v0.2)"

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation

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