A fresh look at retiming via clock skew optimization

Deokar, R.B.; Sapatnekar, Sachin S.

doi:10.1145/217474.217547

Cited by 30 publications

(17 citation statements)

References 11 publications

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“…Introduction of clock skew to an edge-triggered flip-flop has an effect similar to the circuit retiming in VLSI timing optimization-movement of the flip-flops across combinational logic module boundaries [39]. Although it achieves time borrowing as SEFF does, but it makes physical design flow more complex, and in some cases, the standard tools require modification to support clock skew technique.…”

Section: Related Workmentioning

confidence: 99%

Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing

Ghasemazar

Pedram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-in this paper we present and solve the problem of power-delay optimal soft linear pipeline design. The key idea is to use soft-edge flip-flops to allow time borrowing between consecutive stages of the pipeline in order to provide the timingcritical stages with more time to complete their computations. We formulate the problem of optimally designing the soft-edge flipflops and setting the clock frequency and supply voltage so as to minimize the power-delay metric of a pipeline under scenarios using deterministic or statistical delay models. In the first problem formulation, timing violations are avoided by respecting the deterministic worst case path delays. Next, the same problem is formulated for a scenario where stage delays are assumed to be random variables, and we minimize power-delay product while limiting the probability of timing violations in pipeline. The softedge flip flops are equipped with dynamic error detection (and correction) circuitry to detect and fix the errors that might arise from over-clocking. Although the system is capable of recovering from the errors, there is a trade-off between performance and power saving, which is exploited to further minimize the powerdelay product of the pipeline circuit in our third proposed algorithm. Experimental results show the efficacy of our proposed solution techniques for each scenario.Index Terms-Power optimal pipeline design, soft edge flip flops, time borrowing, soft pipeline, power-delay product.

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Section: Related Workmentioning

confidence: 99%

Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing

Ghasemazar

Pedram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…With the introduction of the ASTRA algorithm [6] an alternative view of retiming using the equivalence between retiming and clock skew optimization was proposed. The MINARET algorithm [7] uses the linear programming formulation and incorporates the ASTRA approach to reduce the number of variables and constraints.…”

Section: Improved Techniquesmentioning

confidence: 99%

Integration of retiming with architectural floorplanning

Tabbara

Brayton

et al. 2000

Integration

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“…Retiming was performed to satisfy the constraint on the number of registers on each wire while minimizing the total area of the components. In the paper [15], a clock skew solution corresponding to an optimal clock period was converted into a retiming solution which was guaranteed to be at most one gate delay larger than the optimal clock period. However, their current approach to perform this conversion considered only gate delay.…”

Section: Introductionmentioning

confidence: 99%

Wire Retiming Problem With Net Topology Optimization

Tong

Young

Chu

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we study the retiming problem of sequential circuits with net topology optimization. Both interconnect and gate delay are considered in retiming. Most previous retiming algorithms have assumed ideal conditions for the nonlogical portions of data paths, which are not sufficiently accurate to be used in high performance circuits today. In our modeling, we assume that the delay of a wire is directly proportional to its length. This assumption is reasonable since the quadratic component of a wire delay is significantly smaller than its linear component when the more accurate Elmore delay model is used. A simple experiment was conducted to illustrate the validity of this assumption. We present two approaches to solve the retiming problem, both of which have polynomial time complexity. The first one can compute the optimal clock period while the second one is an improvement over the first one in terms of practical applicability. The second approach gives solutions very close to the optimal (0.06% more than the optimal on average) but in a much shorter runtime. The optimally retimed circuit will then be realized physically by placing the registers and finding the net topologies. In contrast to many previous works [1], [2] that performed simple calculations to determine the register positions, our approach can preserve the optimal clock period obtained by the retiming step and utilize as few registers as possible. Minimization of register number saves both area and power in register and clock loading. Our topology optimization step is shown to be optimal for nets with four or fewer pins and this type of nets constitutes over 90% of the nets in a sequential circuit on average.Using the ISCAS89 benchmark, we tested our algorithm with a 0.35µm CMOS standard cell library. Silicon Ensemble was used to layout the design with row utilization of 50%. Experimental results showed that our algorithm could find the best sharing of registers for a net in most of the cases, i.e., using the minimum number of registers while preserving the target clock period obtained by the retiming step, within a minute run on an Intel Pentium IV 1.5GHz PC with 512MB RAM.

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A fresh look at retiming via clock skew optimization

Cited by 30 publications

References 11 publications

Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing

Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing

Integration of retiming with architectural floorplanning

Wire Retiming Problem With Net Topology Optimization

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