A frequency-scalable 15-bit incremental ADC for low power sensor applications

Abstract

Abstract-A 15-bit low-power incremental ADC is designed for sensor applications. The ADC is designed to be frequency-scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0.35mm 2 . Configured to operate at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83μW from a 1.8-V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/s to 1.67kS/s and scaling analog power by up to 500 times.

A Low-Power CT Incremental 3rd Order <formula formulatype="inline"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> ADC for Biosensor Applications

“…As the process only allowed a maximum device length of 10 µm, each transistor (W/L = 160/32) in the aforementioned differential pair consisted of a stack of four transistors with W/L = 160/8, increasing, as a consequence, their layout and matching complexity. One of the features of IΣ∆ ADCs is their scalability in terms of bandwidth, resolution and power consumption [7], [9]. For the implemented IΣ∆ ADC, scalability is presented by increasing the ADC's bandwidth at a cost of a reduction in performance.…”

“…Furthermore, cascade-ofintegrators in feed-forward (CIFF) configuration with input signal feed-forward has been used to relax the signal swing in the integrators path and minimize the performance degradation due to coefficient variations. With the exception of [7], this has been the preferred configuration for all other implementations and is specially attractive in this work due to the wide integrators' coefficient spread when employing a CT loop filter. All previous incremental implementations, but [2], have used a single bit implementation.…”

“…In particular, high-order architectures are especially attractive from a power consumption perspective, as they reduce the number of cycles per conversion, N . While high-order loop-filter topologies have been used in discrete-time (DT) IΣ∆ ADCs' implementations [2], [7], [8], only first-order topologies architectures have been proposed for continuous time (CT) IΣ∆ ADCs' implementations [1], [9]. On the order hand, highorder CT topologies have been employed in several traditional Σ∆ ADCs [10], [11] to exploit their advantage in terms of power dissipation.…”

“…So far, highorder CT IΣ∆ ADCs have not been implemented but only been investigated in [12] for single-loop (SL) architectures and in [6] for cascaded counterparts. Compared to high-order DT IΣ∆ ADCs [2], [7], [8], a CT implementation would benefit from the aforementioned advantages possibly leading to a low-power implementation. However, it would also impose difficulties which are not present in a DT implementation, such as wider integrators' coefficients spread and increased sensitivity to excess-loop-delay and jitter.…”

On Continuous-Time Incremental $\Sigma\Delta$ ADCs With Extended Range

“…However, they differ from traditional ΣΔ ADCs in that they are able to process time multiplexed signals, acting as a highresolution Nyquist ADC. In particular, high-order single-loop (SL) discrete-time (DT) topologies have been implemented [4]- [6], with the aim of reducing the required number of cycles per conversion N . This allows either to increase the ADC's bandwidth or to reduce the modulator's sampling frequency, which, in turn, reduces the power dissipation.…”