A Frequency-Domain Analysis of Latch Comparator Offset due to Load Capacitor Mismatch

Tao, Yonghong; Hierlemann, Andreas; Lian, Yong

doi:10.1109/tcsii.2015.2406832

Cited by 4 publications

(2 citation statements)

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“…The inherent offset voltage due to device mismatch in the basic static latch circuit has been largely discussed in previous works [8,16,17]. It has been shown that, when assuming perfect matching between the circuit devices, the remaining offset voltage due to the capacitor mismatch at the latch output nodes can be written as…”

Section: Designing the Latch Comparatormentioning

confidence: 99%

“…The inherent offset voltage due to device mismatch in the basic static latch circuit has been largely discussed in previous works [8, 16, 17]. It has been shown that, when assuming perfect matching between the circuit devices, the remaining offset voltage due to the capacitor mismatch at the latch output nodes can be written as

V_{OS} = \frac{1}{2} \frac{I_{0}}{g_{m}} \frac{normalΔ C}{C_{T}}

where I 0 is the average bias current, g m is the average transconductance of the latch devices, Δ C is the output capacitor imbalance and C T is the mean value of the total output capacitor.…”

Section: Designing the Latch Comparatormentioning

confidence: 99%

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Design optimisation procedure for digital mismatch compensation in latch comparators

Khanfir

Mouine²

2018

IET Circuits, Devices & Systems

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Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal-oxide-semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.

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Section: Designing the Latch Comparatormentioning

confidence: 99%

“…The inherent offset voltage due to device mismatch in the basic static latch circuit has been largely discussed in previous works [8, 16, 17]. It has been shown that, when assuming perfect matching between the circuit devices, the remaining offset voltage due to the capacitor mismatch at the latch output nodes can be written as

V_{OS} = \frac{1}{2} \frac{I_{0}}{g_{m}} \frac{normalΔ C}{C_{T}}

where I 0 is the average bias current, g m is the average transconductance of the latch devices, Δ C is the output capacitor imbalance and C T is the mean value of the total output capacitor.…”