A framework for testability metrics across hierarchical levels of assembly

Davidson, Scott; Ungar, Louis Y.

doi:10.1109/autest.2009.5314030

Cited by 4 publications

(1 citation statement)

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“…One test that would probably be available at a time when design changes can be implemented is the design verification test (DVT). In a parallel paper, A Framework for Testability Metrics Across Hierarchical Levels of Assembly, [18] we investigate utilizing simulation techniques to arrive at testability metrics. In future efforts, we will look to incorporate SPOTS into existing ATPG systems.…”

Section: Left Untestedmentioning

confidence: 99%

Simplified metrics for evaluating designs for testability

Ungar

Davidson

2009

2009 Ieee Autotestcon

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Design for Testability (DFT) evaluation is quite complex and circuit dependent. To simplify the analysis and to apply the methodology more generally to different circuit types and different levels of assembly, we focus our efforts on identifying areas of poor testability. We introduce metrics we call Sensitized Path Oriented Testability Scoring TM or SPOTS TM , performed at all points where failure modes are to be detected and diagnosed, to spot poor testability. Once the problem is identified early in the design stage, especially when it is correlated with a circuit node and a failure mode, the remedy needed to correct the problem through DFT can be quite practical. SPOTS measures four testability attributescontrollability, distinguishability, test resource costs, and test escapes due to lack of testability. The metrics simplify previous testability techniques, by utilizing sensitized paths to measure circuit controllability. The use of sensitized paths greatly reduces the analysis required, and while it may not offer validation of testability, it succeeds in highlighting areas that lack testability. Controllability metric (CM) provides a number corresponding to the number of steps required to sensitize a path. Distinguishability metric (DM) measures the difficulty of isolating one fault from others. Test resource cost (RC), includes test program set (TPS) development costs and test equipment requirements, and is expressed in monetary currency. Penalty cost (PC) measures in currency the cost incurred for nodes left untested by escaping detection in tests.Associating each of these metrics to failure modes at each node creates a table that reveals where testability problems exist. Designers and testability analysts can work together to resolve them either by altering the fault detection and isolation requirements, improving test resources and/or redesigning the unit under test (UUT). This form of analysis is simpler to use and is applicable to any level of assembly -IC, board or system. It can even be utilized by those procuring commercial off the shelf (COTS) products to compare support costs for competing products.

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Section: Left Untestedmentioning

confidence: 99%