A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio

Abstract

The genetic algorithm (GA) is an optimization metaheuristic that relies on the evolution of a set of solutions (population) according to genetically inspired transformations. In the variant of this technique called cellular GA, the evolution is done separately for subgroups of solutions. This paper describes a hardware framework capable of efficiently supporting custom accelerators for this metaheuristic. This approach builds a regular array of problem-specific processing elements (PEs), which perform the genetic evolution, connected to shared memories holding the local subpopulations. To assist the design of the custom PEs, a methodology based on highlevel synthesis from C++ descriptions is used. The proposed architecture was applied to a spectrum allocation problem in cognitive radio networks. For an array of 5×5 PEs in a Virtex-6 FPGA, the results show a minimum speedup of 22× compared to a software version running on a PC and a speedup near 2000× over a MicroBlaze soft processor.

Research on Soft Computing Techniques for Cognitive Radio

“…Soucha et al (Soucha, Lamnari & Benatchba, 2013) applied GA to select the optimal transmission parameters and found satisfactory convergence speed. In 2013, Santos et al (Santos, Alves & Ferrira, 2013) proposed a hardware framework capable of efficiently supporting custom accelerators & applied to spectrum allocation problem in CRN. They have demonstrated that, by using an array of 5 X 5 PCs in a vertex-6 FPGA, a minimum speed up of 22 compared to a software version running on a PC & a speed up near 2000 over a micro-Blaze soft processor.…”

Automated framework for FPGA-based parallel genetic algorithms

“…In addition to a considerable number of conventional GA systems mentioned in [4], [5], [6], [20], FPGA-based master-slave GAs and dGAs have been demonstrated [7], [8], [9], [10], [11]. FPGA-based cGAs are also proposed in [12], [13], [14]. In the top 6 rows of Table II we summarise the features of these existing pGA systems.…”

“…There have been previous attempts to adapt pGAs to FPGAs for acceleration or low power consumption [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. However, designing an FPGA-based pGA is not as easy as implementing multiple hardware blocks supporting a set of GA instances.…”

“…As the search processes of GA instances are conducted in different areas of the search space, pGAs can both decrease execution time and improve the quality of solutions [1]. However, CPU-based pGAs may need acceleration for real-time problems, and are not suitable for embedded systems due to the high power consumption [14].…”