Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation 2014
DOI: 10.1145/2594291.2594342
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A framework for enhancing data reuse via associative reordering

Abstract: The freedom to reorder computations involving associative operators has been widely recognized and exploited in designing parallel algorithms and to a more limited extent in optimizing compilers.In this paper, we develop a novel framework utilizing the associativity and commutativity of operations in regular loop computations to enhance register reuse. Stencils represent a particular class of important computations where the optimization framework can be applied to enhance performance. We show how stencil oper… Show more

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Cited by 43 publications
(46 citation statements)
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“…More recently, extensions to the polyhedral framework have been proposed, allowing it to capture reduction computations [11,17,48]. Such efforts are described in [13], but they are fragile in the presence of non static control flow.…”
Section: Related and Future Workmentioning
confidence: 99%
“…More recently, extensions to the polyhedral framework have been proposed, allowing it to capture reduction computations [11,17,48]. Such efforts are described in [13], but they are fragile in the presence of non static control flow.…”
Section: Related and Future Workmentioning
confidence: 99%
“…More recently, extensions to the polyhedral framework have been proposed, allowing it to capture some reduction computations [8,14,32]. Such efforts are described in [12].…”
Section: Related Workmentioning
confidence: 99%
“…This optimization exploits data reuse, thus improving memory hierarchy performance, while also eliminating redundant floating-point computation. Reducing floating-point computation is particularly valuable for large higher-order stencils, as they can be compute bound, and their computation can also stress the register capacity [15].…”
Section: Introductionmentioning
confidence: 99%
“…• We describe the partial sum optimization within the CHiLL compiler [18], which goes beyond related manual [19][20][21] and compiler optimizations [14,15] by simultaneously addressing DRAM and cache bandwidth while reducing floating-point computation and facilitating SIMDization.…”
Section: Introductionmentioning
confidence: 99%