A framework for dynamic energy efficiency and temperature management

Abstract

While technology is delivering increasingly sophisticated and powerful chip designs, it is also imposing alarmingly high energy requirements on the chips. One way to address this problem is to manage the energy dynamically. Unfortunately, current dynamic schemes for energy management are relatively limited. In addition, they manage energy either for energy efficiency or for temperature control, but not for both simultaneously.In this paper, we design and evaluate for the first time an energymanagement framework that tackles both energy efficiency and temperature control in a unified manner. We call this general approach Dynamic Energy Efficiency and Temperature Management (DEETM). Our framework combines many energy-management techniques and can activate them individually or in groups in a finegrained manner according to a given policy. The goal of the framework is two-fold: maximize energy savings without extending application execution time beyond a given tolerable limit, and guarantee that the temperature remains below a given limit while minimizing any resulting slowdown. The framework successfully meets these goals. For example, it delivers a 40% energy reduction with only a 10% application slowdown.

Thermal-aware clustered microarchitectures

“…Huang et al [14] propose a framework to maximize energy savings and to guarantee that temperature remains under a certain threshold. The framework combines a number of energy-management techniques.…”

Energy reduction in multiprocessor systems using transactional memory

“…The energy consumption of a single cache is thus a factor of its implementation (SRAM vs. DRAM), its size, the capacitance of the busses it drives (which depend on whether the cache is on or off-chip), as well as the number of read and write accesses. The dominant portion of energy consumption per access in the memory hierarchy is due to off-chip caches, resulting from their significantly larger size, and the higher capacitance board buses [3], [8]. The largest and most remote memory in a multiprocessor system is the shared memory.…”

Low-Overhead Core Swapping for Thermal Management

“…They also compared commonly used DTM techniques such as clock frequency scaling, voltage and frequency scaling, decode throttling, speculation control and instruction cache toggling [8]. An energymanagement framework that combines energy efficiency and temperature management, DEETM, was presented by Huang et al [25]. They propose several power optimization techniques such as global clock gating, DVS, sub-banking, filtered instruction cache.…”

“…In recent years, dynamic thermal management (DTM) [4,8,14,25,15] has become an integral part of microprocessor design to adapt to increasing on-chip temperatures. The disparity between the maximum possible power dissipation and typical power dissipation has become more pronounced.…”