A framework for developing parametrised FPGA libraries

Pebble: A language for parametrised and reconfigurable hardware design

“…The two primary objectives for Pebble are to facilitate the development of efficient and reusable designs, and to support the development of designs involving run-time reconfiguration. Much of our previous work is based on VHDL, which has been used for both library development [7] and simulation of reconfigurable components [11].…”

“…2, provided that the size parameter n is 4. In more complex descriptions, the parameters in a Pebble program can include the number of pipeline stages or the pitch between neighbouring interface connections [7]. Different network structures, such as tree-or butterfly-shaped circuits, can be described parametrically by indexing the components and wires.…”

“…Pebble programs can be compiled into the netlist format for the Rebecca simulator, which can be used for cycle-accurate numerical or symbolic simulation at wordlevel, bit-level, or a mixture [7]. Automatic mapping between word-level and bit-level blocks is under development.…”

“…These components are developed carefully to ensure that they are efficient, validated and easy to use. Several development systems based on Java [1], Lola [2], C [3], ML [5], VHDL and Ruby [7] have been proposed. While the languages in these systems have their own goals and merits, none seems to meet all our requirements of:…”

“…having a simple syntax and semantics; 2. allowing a wide range of parameters in design descriptions; 3. providing support for both word-level design and bit-level design; 4. supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; 5. including facilities for developing designs reconfigurable at run time. From our previous work [7] and others, it is also important for design tools to:…”