A framework for determining useful parallelism

Allen, Frances E.; Burke, Michael G.; Cytron, Ron K.; Ferrante, Jeanne; Hsieh, Wilson C.

doi:10.1145/55364.55385

Cited by 54 publications

(12 citation statements)

References 10 publications

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“…In this extended replication transformation, called full replication, we create copies that are local to the loops that both read and write the arrays. 1 We trade decreased execution time for increased array storage. In addition, the implementation must update the arrays to ensure data consis- tency.…”

Section: Examplementioning

confidence: 99%

“…Many compilers targeting shared memory systems replicate data to enable concurrent read accesses [1] and further [8] investigates adaptive replication in order to reduce synchronization overheads that may ultimately degrade performance. Memory Parallelism There have been many approaches to improve memory parallelism.…”

Section: Replication For Shared Memory Multiprocessor Systemsmentioning

confidence: 99%

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Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures

Ziegler

Malusare

Diniz

2006

Languages and Compilers for Parallel Computing

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Abstract. Configurable architectures, with multiple independent onchip RAM modules, offer the unique opportunity to exploit inherent parallel memory accesses in a sequential program by not only tailoring the number and configuration of the modules in the resulting hardware design but also the accesses to them. In this paper we explore the possibility of array replication for loop computations that is beyond the reach of traditional privatization and parallelization analyses. We present a compiler analysis that identifies portions of array variables that can be temporarily replicated within the execution of a given loop iteration, enabling the concurrent execution of statements or even non-perfectly nested loops. For configurable architectures where array replication is essentially free in terms of execution time, this replication enables not only parallel execution but also reduces or even eliminates memory contention. We present preliminary experiments applying the proposed technique to hardware designs for commercially available FPGA devices.

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Section: Examplementioning

confidence: 99%

Section: Replication For Shared Memory Multiprocessor Systemsmentioning

confidence: 99%

Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures

Ziegler

Malusare

Diniz

2006

Languages and Compilers for Parallel Computing

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“…Our memory model assumes there will be no conflict or capacity cache misses in one iteration of the innermost loop. 1 The algorithm performs the following five steps:…”

Section: Optimize: Data Locality and Parallelismmentioning

confidence: 99%

“…Many commercial parallelizing compilers do not reveal their optimization strategies to maintain a market advantage. The IBM PTRAN project, an industrial research compiler, has published parallelization algorithms that use control and data dependence, and a wide selection of transformations, but without results [1], [40], [41]. Below, we compare this study with those of parallelizing compilers from Illinois and Stanford [10], [17], [19], [43].…”

Section: Related Workmentioning

confidence: 99%

A compiler optimization algorithm for shared-memory multiprocessors

McKinley

1998

IEEE Trans. Parallel Distrib. Syst.

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This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, shared-memory multiprocessors. The algorithm considers data locality, parallelism, and the granularity of parallelism. It uses dependence analysis and a simple cache model to drive its optimizations. It also optimizes across procedures by using interprocedural analysis and transformations. We validate the algorithm by hand-applying it to sequential versions of parallel, Fortran programs operating over dense matrices. The programs initially were hand-coded to target a variety of parallel machines using loop parallelism. We ignore the user's parallel loop directives, and use known and implemented dependence and interprocedural analysis to find parallelism. We then apply our new optimization algorithm to the resulting program. We compare the original parallel program to the hand-optimized program, and show that our algorithm improves three programs, matches four programs, and degrades one program in our test suite on a shared-memory, bus-based parallel machine with local caches. This experiment suggests existing dependence and interprocedural array analysis can automatically detect user parallelism, and demonstrates that user parallelized codes often benefit from our compiler optimizations, providing evidence that we need both parallel algorithms and compiler optimizations to effectively utilize parallel machines.

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“…Classic methods [7,8,11,14,24] have lots of problems to identify parallel opportunities outside nested loops. The latest researches in this field [10,5,6], based on pattern-maching techniques, allows to substitute part of a sequential program by an equivalent parallel subprogram.…”

Section: Introductionmentioning

confidence: 99%

Parallel Execution of For Loops Using Checkpointing Techniques

Renault

2005 International Conference on Parallel Processing Workshops (ICPPW'05)

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Checkpointing techniques have been used to secure sequential and parallel programs for many years. In this article, we show how checkpointing techniques can be used in order to transform and execute for loops of sequential programs on a parallel machine, especially on a cluster or on a grid. This article also presents the implementation we have developed to valid the concept and some performance measurements.

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A framework for determining useful parallelism

Cited by 54 publications

References 10 publications

Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures

Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures

A compiler optimization algorithm for shared-memory multiprocessors

Parallel Execution of For Loops Using Checkpointing Techniques

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