A Framework for Design, Verification, and Management of SoC Access Control Systems

Restuccia, Francesco; Meza, Andrés; Kastner, Ryan; Oberg, Jason

doi:10.1109/tc.2022.3209923

Cited by 5 publications

(1 citation statement)

References 30 publications

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“…All these sub-systems are part of NoC and it is integrated as SoC systems for interfacing with high speed Cortex-M33 processors and other controllers through different protocols [23]. In Algorithm 1, the first step is for FG creations, from which, the input packet includes both information data and destination id as labels and FG contains the number of edges and capacity determination [24]. All edges in FG will change their directions from 𝐸 𝑖𝑗 to 𝐸 𝑗𝑖, based on the next router which is depending on the destination node.…”

Section: Proposed Low Power Router Design For Label Switching-noc'smentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

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Section: Proposed Low Power Router Design For Label Switching-noc'smentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

View full text Add to dashboard Cite

show abstract

Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips

Restuccia,

Kastner

2024

2024 IEEE 3rd Real-Time and Intelligent Edge Computing Workshop (RAGE)

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Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies

Meza

Kastner

2023

Proceedings of Cyber-Physical Systems and Internet of Things Week 2023

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A Framework for Design, Verification, and Management of SoC Access Control Systems

Cited by 5 publications

References 30 publications

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips

Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies

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