A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy

Bhattacharya, Koustav; Ranganathan, N.; Kim, Soontae

doi:10.1109/tvlsi.2008.2003236

Cited by 23 publications

(16 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Zhang et al [9] investigate impacts of soft errors on processor caches, and introduce the cache vulnerability factor (CVF) to soft errors and proposed two early write back methods for reducing this vulnerability. Bhattacharya et al [21] consider multi-bit errors, and propose an adaptive scheme for correcting them errors relaying on the data replication that exists in the memory subsystem. Li et al [22] propose an effective adaptive error protection scheme for chip-multiprocessor busses that adapts to the amount of noise present in the environment.…”

Section: B Hardware Based Error Detection and Correctionmentioning

confidence: 99%

Analyzing the soft error resilience of linear solvers on multicore multiprocessors

Malkowski

Raghavan

Kandemir

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing (IPDPS)

View full text Add to dashboard Cite

As chip transistor densities continue to increase, soft errors (bit flips) are becoming a significant concern in networked multiprocessors with multicore nodes. Large cache structures in multicore processors are especially susceptible to soft errors as they occupy a significant portion of the chip area. In this paper, we consider the impacts of soft errors in caches on the resilience and energy efficiency of sparse linear solvers. In particular, we focus on two widely used sparse iterative solvers, namely Conjugate Gradient (CG) and Generalized Minimum Residuals (GMRES). We propose two adaptive schemes, (i) a Write Eviction Hybrid ECC (WEH-ECC) scheme for the L1 cache and (ii) a Prefetcher Based Adaptive ECC (PBA-ECC) scheme for the L2 cache, and evaluate the energy and reliability trade-offs they bring in the context of GMRES and CG solvers. Our evaluations indicate that WEH-ECC reduces the CG and GMRES soft error vulnerability by a factor of 18 to 220 in L1 cache, relative to an unprotected L1 cache, and energy consumption by 16%, relative to a cache with strong protection. The PBA-ECC scheme reduces the CG and GMRES soft error vulnerability by a factor of 9 × 10 3 to 8.6 × 10 9 , relative to an unprotected L2 cache, and reduces the energy consumption by 8.5%, relative to a cache with strong ECC protection. Our energy overheads over unprotected L1 and L2 caches are 5% and 14% respectively.

show abstract

Section: B Hardware Based Error Detection and Correctionmentioning

confidence: 99%

Analyzing the soft error resilience of linear solvers on multicore multiprocessors

Malkowski

Raghavan

Kandemir

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing (IPDPS)

View full text Add to dashboard Cite

show abstract

“…To prevent latency increasing, first level (L1) caches tend to employ parity check codes that allow bit error detection, but no correction. Bhattacharya et al investigate in detail multi-bit soft error rates in large L2 caches and propose a framework based on the amount of redundancy present in the memory hierarchy [11]. Despite the fact that most of the previous work has studied effectiveness in terms of performance, energy, and area overheads, it targets data bits reliability with the assumption that tag bits are intact.…”

Section: By Our Experiments With Embedded Benchmarks On An Intelmentioning

confidence: 99%

SimTag: Exploiting tag bits similarity to improve the reliability of the data caches

Kim¹,

Kim²,

Lee³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

View full text Add to dashboard Cite

Though tag bits in the data caches are vulnerable to transient errors, few effort has been made to reduce their vulnerability. In this paper, we propose to exploit prevalent same tag bits to improve error protection capability of the tag bits in the data caches. When data are fetched from the main memory, it is checked if adjacent cache lines have the same tag bits as those of the data fetched. This similarity information is stored in the data caches as extra bits to be used later. When an error is detected in the tag bits, the similarity information is used to recover from the error in the tag bits. The proposed scheme has small area, energy, and performance overheads with error protection coverage of 97.9% on average. In contrast, the previously proposed In-Cache Replication scheme is shown to incur large performance and energy overheads.I.

show abstract

“…The rate of spatial multi-bit errors increases across technology generations as device feature sizes shrink. This is because due to the higher packing of the cells in the same active area, a single radiation strike can now affect multiple cells simultaneously, potentially leading to multi-bit errors [4]. Multi-bit errors can also arise over time.…”

Section: Introductionmentioning

confidence: 99%

“…For example, ZHANG et al [11] proposed a small fully-associative cache named replication cache to store the replicas to correct the data blocks affected by errors. BHATTACHARYA et al [4] proposed to exploit small data values, which use at most half of the memory word bits, to increase redundancy and improve the reliability of the L2 cache. The small data values can be duplicated in their upper half of the memory word bits, which increases the degree of redundancy in the L2 cache.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

Wang

Liu

Chen

2015

J. Cent. South Univ.

View full text Add to dashboard Cite

Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.

show abstract

A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy

Cited by 23 publications

References 29 publications

Analyzing the soft error resilience of linear solvers on multicore multiprocessors

Analyzing the soft error resilience of linear solvers on multicore multiprocessors

SimTag: Exploiting tag bits similarity to improve the reliability of the data caches

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

Contact Info

Product

Resources

About