A framework for application guidance in virtual memory systems

Jantz, Michael R.; Strickland, Carl; Kumar, Karthik; Dimitrov, Martin; Doshi, Kshitij

doi:10.1145/2451512.2451543

Cited by 18 publications

(2 citation statements)

References 15 publications

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“…Some methods try to maintain the predictability of the real‐time systems through scheduling the requests of various cores to access shared memory at the operating system (OS) level [25, 26]. These methods utilise a DRAM bank‐level partitioning algorithm in an OS kernel such as Linux.…”

Section: Related Workmentioning

confidence: 99%

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Dabaghi¹,

Farbeh²

2019

IET Computers & Digital Techniques

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Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.

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Section: Related Workmentioning

confidence: 99%

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Dabaghi¹,

Farbeh²

2019

IET Computers & Digital Techniques

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“…Janz et al [34] propose a software scheduling framework in which an application interacts with the OS to determine its dynamic memory footprint utilization. In this report, memory thread scheduling is not approached, therefore Xie's and Janz' techniques can be orthogonally applied to RF iop.…”

Section: Power and Energy Analysesmentioning

confidence: 99%

Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability

Marino

2018

IEEE Trans. VLSI Syst.

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Abstract-Despite power boundaries, Moore's law is still present via scaling the number of cores, which keeps adding demands for more memory bandwidth requested by these cores. To obtain higher bandwidth levels it is fundamental to address memory controller (MC) scalability. However, MC scalability growth is limited by I/O pin counts scaling. To underline MC and pin scaling, a radio frequency( RF) I/ O pad-scalable packagebased (RF iop) memory organization is further investigated.In RF iop, a radio-frequency pad (RFpad) is defined as a quilt-packaging (QP) coplanar waveguide (CPW) employed at radio-frequency (RF) ranges. An RFpad connects a rank to an RFMC which is formed by coupling MCs to RF TX/RX. By using QP package to explore the architectural benefits of laying out ranks, RF iop replaces the traditional memory path with an RFbased one, whilst exploring the scalability of RFpads/RFMCs via RF signaling. When evaluating RF iop, our findings show that bandwidth/performance are enhanced by around 4.3x which can be viewed as a diminution in transaction queue occupancy/latency as well as using a reduced and scalable 4-8 RFpads per RFMC. RF iop architectural area benefits allow bandwidth/performance improvements of around 3.2x, whilst reducing interconnection energy up to 78%.

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