A fractional-N PLL with small Δ<i>K</i><sub>vco</sub>wideband LC-VCO and current-matching CP for M-DTV systems

Gao, Haijun; Yan, Yihua; Du, Zhen‐Ting; Guo, Guiliang; Longyue, Zeng

doi:10.1080/00207217.2011.567033

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…As shown in Fig. 5, due to the negative feedback effect of the operational amplifier, the leakage voltage of the bias tube at the output end of the charge pump in the circuit is always equal to that of the bias tube in the reference bias circuit, so the current of UP and DOWN can follow the current of the reference source accurately [10]. As the current flowing through the two bias tubes is always equal, the UP current and the DOWN current will not be affected by the variation of output voltage, thus ensuring good dynamic and static linearity of the charge pump.…”

Section: Charge Pump Designmentioning

confidence: 99%

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

Liu

Chai

Liu

2019

IEICE Electron. Express

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This paper presents a fractional-N frequency synthesizer for ultra high frequency radio frequency identification (UHF RFID) reader application. With the use of a novel parallel dual inductance resonator in the inductance and capacitance based voltage-controlled oscillator (LC_VCO), the resonator cavity loss was greatly reduced as well as the temperature drift was suppressed. At the same time, the loop linearity is improved by the use of operational amplifier tracking technology. The chip is fabricated in a 0.13 µm RF CMOS technology with a single 1.2 V power supply. The synthesizer provides a tuning range from 840 MHz to 960 MHz. The worst phase noise of −95 dBc/Hz in band, −110 dBc/Hz@100 kHz offset, −135 dBc/Hz@1 MHz offset with a reference spur of −78 dBc are measured at a center frequency of 920.125 MHz. A 0.95 ps integrated RMS jitter and an 18.5 mW power dissipation are obtained at a temperature range from −40°C to 85°C.

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Section: Charge Pump Designmentioning

confidence: 99%

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

Liu

Chai

Liu

2019

IEICE Electron. Express

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“…Fractional-N PLL use Dual Modulus Prescalers to enable fractional divide-by ratio in the feedback loop of the PLL. Dual modulus pre scalers also scale down the high output frequency (GHz) of the PLL before its divided by the main divider in the feedback loop ( [3], [4]). Hence Dual Modulus Prescalers have to take in a high frequency (typically GHz) and divide it with minimum hardware and power consumption.…”

Section: Introductionmentioning

confidence: 99%

A low power dual modulus prescaler for fractional-N PLL synthesizer

Zackriya

Reuben

Kittur

2014

2014 International Conference on Electronics and Communication Systems (ICECS)

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Phase Locked Loop (PLL) based frequency synthe-sizers are widely used to generate spectrally pure clock references for the cores in System-on-Chips (SoCs). Fractional-N PLL has evolved from the basic integer-N PLL to enable high resolution in output frequency. A Dual Modulus Prescaler (DMP) forms an integral part of the feedback circuitry to achieve fractional 'divide-by' ratios. It is also used to scale down the output frequency of Voltage Controlled Oscillator (VCO) for phase and frequency comparisons. Since DMP works at the highest frequency in design strenuous feedback block of a PLL, numerous researchers have proposed various techniques to reduce the power consumption of DMPs. In his paper we first propose a low power FF of True Single Phase Clock type which is then used to construct a DMP. Our proposed 2/3 prescaler works effectively till 12 GHz. Since PLL demands high accuracy, we also simulate our design across the PVT (Process, Voltage, Temperature) variations upto 5 GHz to verify its suitability for frequency synthesis. Our DMP consumes power lesser than 100 W while dividing a 5 GHz clock which is energy efficient compared to others in recent literature.

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Phase-locked loop design with fast-digital-calibration charge pump

Wang

Hwang

Wang

2015

International Journal of Electronics

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A fractional-N PLL with small ΔK_vcowideband LC-VCO and current-matching CP for M-DTV systems

Cited by 7 publications

References 5 publications

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

A low power dual modulus prescaler for fractional-N PLL synthesizer

Phase-locked loop design with fast-digital-calibration charge pump

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A fractional-N PLL with small ΔKvcowideband LC-VCO and current-matching CP for M-DTV systems

Cited by 7 publications

References 5 publications

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

A new method to improve the phase noise performance of the frequency synthesizer for UHF RFID

A low power dual modulus prescaler for fractional-N PLL synthesizer

Phase-locked loop design with fast-digital-calibration charge pump

Contact Info

Product

Resources

About

A fractional-N PLL with small ΔK_vcowideband LC-VCO and current-matching CP for M-DTV systems