IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011) 2011
DOI: 10.1049/cp.2011.0903
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A FPGA ray tracing scheme with memory optimization facility

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“…In the SBR method, the intersection tests are quite time-consuming especially as the target size increasing. Many acceleration techniques, such as ray-box intersection algorithm in FPGA [13,14], multiresolution grid algorithm [15], recursive subdivision octree algorithm [16], and KD-tree based algorithm [17], have been developed to reduce the computation time of ray-tracing process. In this report, the bidirectional ray-tracing algorithm is proposed to decrease the intersection tests between patches and rays, further reducing computation time.…”
Section: Introductionmentioning
confidence: 99%
“…In the SBR method, the intersection tests are quite time-consuming especially as the target size increasing. Many acceleration techniques, such as ray-box intersection algorithm in FPGA [13,14], multiresolution grid algorithm [15], recursive subdivision octree algorithm [16], and KD-tree based algorithm [17], have been developed to reduce the computation time of ray-tracing process. In this report, the bidirectional ray-tracing algorithm is proposed to decrease the intersection tests between patches and rays, further reducing computation time.…”
Section: Introductionmentioning
confidence: 99%