A FPGA Implementation of a Dual-Axis Solar Tracking System

Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model

“…Some of the published research works by Basith et al (2017), Basith et al (2016) and Arrofiqi et al (2015) have reported the implementation of FLC in an embedded Advanced RISC Machines (ARM) microcontroller for wearable closed-loop FES applications such as knee walking cycles and gait control movements [18,42,43]. FLC implementation in a field-programmable gate array (FPGA) has recently piqued the interest of researchers in both linear and non-linear applications to improve control performance [44,48,49]. Since fuzzy logic does not require a complex mathematical model, it is considered easy to implement for real-world FES applications.…”

“…The implementation of FLC as a feedback controller in an embedded system is very important for a wearable closed-loop FES device application [ 18 , 42 , 43 ]. The possible digital controllers that can be used to develop FLC in embedded systems are microcontroller, Digital Signal Processor (DSP), application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) technologies [ 44 , 45 ]. However, microcontroller and DSP have some delays in the memory execution due to their sequential nature of processing, which results in low processing speed for complex algorithms [ 45 , 46 ].…”

“…However, microcontroller and DSP have some delays in the memory execution due to their sequential nature of processing, which results in low processing speed for complex algorithms [ 45 , 46 ]. Therefore, ASIC and FPGA are preferred due to their excellent performance in terms of parallel computations, concurrency, effective real-time implementation and higher speed [ 44 , 47 , 48 , 49 , 50 ]. Hardware Description Language (HDL) Verilog or VHDL is typically employed to implement digital design in ASICs and FPGAs.…”

“…Hardware Description Language (HDL) Verilog or VHDL is typically employed to implement digital design in ASICs and FPGAs. Although ASIC could provide a decent low power consumption rate, the customized hardware does not provide flexibility in reprogramming the chip and is not a cost-effective solution due to longer design cycle duration and higher manufacturing costs [ 44 , 50 ]. In contrast, the FPGA provides flexibility in multiple reprogramming according to current design changes, a shorter design cycle duration that enables rapid prototyping and a cost-effective solution for a broad range of applications [ 44 , 45 , 47 , 48 , 49 ].…”

“…Although ASIC could provide a decent low power consumption rate, the customized hardware does not provide flexibility in reprogramming the chip and is not a cost-effective solution due to longer design cycle duration and higher manufacturing costs [ 44 , 50 ]. In contrast, the FPGA provides flexibility in multiple reprogramming according to current design changes, a shorter design cycle duration that enables rapid prototyping and a cost-effective solution for a broad range of applications [ 44 , 45 , 47 , 48 , 49 ]. Therefore, the implementation of FLC in an FPGA device for closed-loop FES applications provides attractive and promising solutions for efficient hardware design, as well as rapid prototyping.…”