A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor

Abstract

This paper presents the design and implementation of a multiplierless JPEG compressor for gray scale images. The modules of this architecture were fully pipelined and targeted to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to Altera Flex10KE FPGAs. The JPEG compressor pipeline has a minimum latency of 238 clock cycles, given the full modular pipeline depth. The minimum compressor period is 26.6ns and the compressor is able to process 37.6 millions of pixels per second. For example, the compressor can process a 640x480 pixels still image in 8.2ms, reaching a maximum processing rate of 122.4 frames per second.

Design and performance analysis of a zonal DCT-based image encoder for Wireless Camera Sensor Networks

“…Agostini et al [20] proposed an implementation of a JPEG encoder for low-cost and low-power FPGAs. This encoder is based on a fast multiplierless 2-D DCT algorithm with a cost of 704 additions and 304 shifts per block of 8 Â 8 pixels.…”

“…Table 4 summarizes a comparison, of the designed circuit for k¼4, with other implementations of the image compression on FPGA circuits [18,[20][21][22]. In order to get more meaningful comparisons, our proposed image compression scheme had been synthesized, also, for others FPGA devices (Xilinx Spartan-3 XC3S200, Xilinx Virtex-4 XC4VLX15 and Xilinx Virtex-E XCV1600E).…”

“…Only the nearest ones of our proposal are presented here. The works in [20][21][22]13] was targeted to low-cost FPGAs, and the ones in [12,18,[23][24]11] to ASICs. The zonal coding approach was investigated in none of these works, except in [11,13].…”

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops

“…The number of used slices for logic is quite low and leaves room for implementation of the processing elements. We have compared our implementation of a gray-scale JPEG encoder with the manual implementation proposed in [25]. We achieve a throughput of 164 frames of 640×480 pixels compared to a throughput of 122 frames achieved in [25].…”

“…We have compared our implementation of a gray-scale JPEG encoder with the manual implementation proposed in [25]. We achieve a throughput of 164 frames of 640×480 pixels compared to a throughput of 122 frames achieved in [25]. For an area occupancy of 1% of slices and 8% of RAMB16s.…”