A Formal Proof of PG Recurrence Equations of Parallel Adders

Chen, Gang; Song, Xiaoyu; Yang, Guowu; Wang, Ting; Mu, Xiaoqiao; Fan, Yongqian

doi:10.1109/tcad.2020.3015414

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…To compare performance of different circuits, the following performance parameters are considered. 39,40 • Average power consumption: Since different input-output combinations in digital circuits lead to different power dissipations, it becomes necessary to analyze all input-output transitions. After getting power dissipation data of all input-out transition, average value of the power dissipations due to different input-output combinations is taken as the average power of a circuit.…”

Section: Circuit Simulation and Comparison Parametersmentioning

confidence: 99%

“…Supply voltage for all simulations is set to 1 V and frequency is set to 100 MHz. To compare performance of different circuits, the following performance parameters are considered 39,40 Average power consumption: Since different input–output combinations in digital circuits lead to different power dissipations, it becomes necessary to analyze all input–output transitions.…”

Section: Circuit Simulation Parameters In Cadencementioning

confidence: 99%

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Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

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This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

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Section: Circuit Simulation and Comparison Parametersmentioning

confidence: 99%

Section: Circuit Simulation Parameters In Cadencementioning

confidence: 99%

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

View full text Add to dashboard Cite

show abstract

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

Ebrahimi-Azandaryani

Akbari

Kamal

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

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A Formal Proof of PG Recurrence Equations of Parallel Adders

Cited by 2 publications

References 14 publications

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

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