A Formal Model of SysML Blocks Using CSP for Assured Systems Engineering

Jacobs, Jaco; Simpson, Andrew

doi:10.1007/978-3-319-17581-2_9

Cited by 6 publications

(5 citation statements)

References 6 publications

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“…The work described in this paper significantly extends the work of [12] by providing a more comprehensive semantics for both SysML activities and state machines. The purpose of [12] was to demonstrate an integrated semantics for activities and state machines, rather than formulate a comprehensive semantics of each. In this paper we aim to demonstrate a comprehensive, integrated semantics considering both behavioural constructs.…”

Section: Activity Constructmentioning

confidence: 88%

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On the formal interpretation and behavioural consistency checking of SysML blocks

Jacobs

Simpson

2015

Softw Syst Model

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The Systems Modeling Language (SysML) is a semi-formal, graphical modelling language used in the specification and design of systems. We describe how Communicating Sequential Processes (CSP) and its associated refinement checker, FDR3, may be used to underpin an approach that facilitates the refinement checking of the behavioural consistency of SysML diagrams. We achieve this by utilising CSP as a semantic domain for reasoning about SysML behavioural aspects: activities and state machines are given a formal, process-algebraic semantics. These behaviours execute within the context of the structural diagrams to which they relate, and this is reflected in the CSP descriptions that depict their characteristic patterns of interaction. We describe how CSP and FDR3 can be used in conjunction with SysML in a formal, top-down approach to systems engineering. Moreover, the compositionality afforded by CSP alleviates the state space explosion problem frequently encountered with complex formal models, and complements the top-down approach of SysML. Typically, a system is composed from constituent systems using the concept of blocks. SysML permits two alternative interpretations with regards to the behaviour of the resulting composition. We argue that the use of a process-algebraic formalism enables us to explore the relationships between these interpretations in a more rigorous fashion than would otherwise be the case.

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Section: Activity Constructmentioning

confidence: 88%

“…In doing this, we have defined the semantics of state machines and activities that execute within this context. This paper represents a significant extension to the contribution of [12]. The interested reader is referred to [10] for a consideration of how this approach can support formal requirements traceability via refinement checking.…”

Section: Discussionmentioning

confidence: 99%

On the formal interpretation and behavioural consistency checking of SysML blocks

Jacobs

Simpson

2015

Softw Syst Model

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“…We exclude publications related to formalisms close to (but different from) UML state machines. We notably exclude significant extensions of UML, such as krtUML (for which an executable semantics is discussed in [Dam+05]), or SysML (partially formalized in, e.g., [JS14]). The same applies to UML-RT.…”

Section: Criteria For Exclusionmentioning

confidence: 99%

“…SysML is close to UML (in fact the syntax of SysML state machines can be seen as a subset of UML behavioral state machines) and this work is therefore worth mentioning. The UML state machine syntax supported by [JS14] is very limited, but its main interest is that the translation is performed in conjunction with activity diagrams. The event queue seems well encoded.…”

Section: Translation Into Process Algebrasmentioning

confidence: 99%

Formalizing UML State Machines for Automated Verification – A Survey

André

Liu

et al. 2023

ACM Comput. Surv.

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The Unified Modeling Language (UML) is a standard for modeling dynamic systems. UML behavioral state machines are used for modeling the dynamic behavior of object-oriented designs. The UML specification, maintained by the Object Management Group (OMG), is documented in natural language (in contrast to formal language). The inherent ambiguity of natural languages may introduce inconsistencies in the resulting state machine model. Formalizing UML state machine specification aims at solving the ambiguity problem and at providing a uniform view to software designers and developers. Such a formalization also aims at providing a foundation for automatic verification of UML state machine models, which can help to find software design vulnerabilities at an early stage and reduce the development cost. We provide here a comprehensive survey of existing work from 1997 to 2021 related to formalizing UML state machine semantics for the purpose of conducting model checking at the design stage.

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“…The verification is done by automatic transformation from the architectural model to a network of timed automata analysed by UPPAAL. Jacobs and Simpson (2015) present a compositional approach to refinement and specification in the context of SysML. They consider the behavior of SysML blocks as a set of composed behavior of state machine and activity diagrams.…”

Section: Related Workmentioning

confidence: 99%

A quantitative verification framework of SysML activity diagrams under time constraints

Baouya

Bennouar

Mohamed

et al. 2015

Expert Systems with Applications

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a b s t r a c tTime-constrained and probabilistic verification approaches gain a great importance in system behavior validation including avionic, transport risk assessment, automotive systems and industrial process controllers. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. Due to the difficulty of analyzing, modeling and verifying these large scale systems, we introduce a novel verification framework based on PRISM probabilistic model checker that takes the SysML activity diagram as input and produce their equivalent timed probabilistic automata that is/are expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. To prove the soundness of our mapping approach, we capture the underlying semantics of both the SysML activity diagrams and their generated PRISM code. We found that the timed probabilistic equivalence relation between both semantics preserve the satisfaction of the system requirements. We present digital camera as case study to illustrate the applicability of the proposed approach and to demonstrate its efficiency by analyzing a performability properties.

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A Formal Model of SysML Blocks Using CSP for Assured Systems Engineering

Cited by 6 publications

References 6 publications

On the formal interpretation and behavioural consistency checking of SysML blocks

On the formal interpretation and behavioural consistency checking of SysML blocks

Formalizing UML State Machines for Automated Verification – A Survey

A quantitative verification framework of SysML activity diagrams under time constraints

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