A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

“…If the CUT is a synchronous circuit then obviously the online tester is also a synchronous circuit that can be designed from the FD-transitions using straightforward FSM synthesis philosophy [18,19]. The detector FSM has three classes of states, namely, initial, intermediate, and final.…”

“…For example, if we consider only two faults in the circuit under consideration, stuck-on fault in 1 of C2 and stuck-on fault in 1 of C1, then the FD-transition set is {⟨ 11, 6⟩, ⟨ 13, 8⟩, ⟨ 2, 11⟩}. The above mentioned philosophy of constructing the detector and then synthesizing it into a synchronous system is widely used in the DES theory [17] and has been applied for OLT of synchronous circuits [18,19]. Obviously, if the CUT is an asynchronous circuit and so must be the detector circuit.…”

“…For OLT of circuits, the detector is synthesized as a circuit which is executed concurrently with the circuit under test (CUT). Biswas et al in [18,19] have developed an OLT scheme for synchronous circuits using the FSM based DES theory, which satisfies most of the metrics mentioned above for an efficient online tester design. In this paper, we aim at using the theory of failure detection of DES models for OLT of SI circuits.…”

“…Several modifications are made in the DES framework used for synchronous circuits [18,19] when applied for SI circuits. The modifications are as follows:…”

“…A synchronous circuit can be synthesized in a straightforward way from the FSM specification [18,19] that performs online testing. Why the same design cannot be synthesized as an asynchronous circuit will be discussed in this paper.…”