A fluxless bonding process using AuSn or Indium for a miniaturized hermetic package

Volpert, Marion; Kopp, Christophe; Routin, Julien; Gasse, A.; Bernabé, Stéphane; Rossat, C.; Tournair, Myriam; Hamelin, R.; Lecocq, Vincent

doi:10.1109/ectc.2009.5074021

Cited by 11 publications

(5 citation statements)

References 6 publications

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“…With 4 μm of originally deposited indium, a reflow process under formic acid and at a temperature above 180 • C is used to form 10-20 μm high bumps which were then bonded to metalized pads [7]. Using a reflow process at 180 • C under an active atmosphere of H 2 N 2 before bonding, indium bonds pass the gross leak test with isopropanol [8]. Localized bonding with an evaporated indium solder as an intermediate layer was realized either with a poly-silicon microheater underneath the indium solder to heat it up to 300 • C [9] or by introducing a nanofoil T M as the heat source [10].…”

Section: Introductionmentioning

confidence: 99%

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging

Straessle

Pétremand

Briand

et al. 2013

J. Micromech. Microeng.

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This paper reports on low-temperature and hermetic thin-film indium bonding for wafer-level encapsulation and packaging of delicate and temperature sensitive devices. This indium-bonding technology enables bonding of surface materials commonly used in MEMS technology. The temperature is kept below 140 °C for all process steps and no surface treatment is applied before and during bonding. This bonding technology allows hermetic sealing at 140 °C with a leak rate below 4 × 10−12 mbar l s−1 at room temperature. The tensile strength of the bonds up to 25 MPa goes along with a very high yield.

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Section: Introductionmentioning

confidence: 99%

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging

Straessle

Pétremand

Briand

et al. 2013

J. Micromech. Microeng.

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“…Some people attribute these voids to tin oxide, contaminations or to Kirkendall voids due to inter-metallic formation [4], and solve the problem with a plasma surface activation before bonding [6], an aging of samples at 200°C or an active atmosphere during reflow [4][5] [7]. Voids also come from the pores in the AuSn ECD process.…”

Section: Studymentioning

confidence: 99%

“…Well known at die level for optoelectronic devices [4][5], it is now demonstrated at wafer level for RF MEMS [2] [6]. In these cases, 3 to 5/lm-thick solder joints are fabricated by PVD and lift-off processes.…”

Section: Introductionmentioning

confidence: 99%

Hermetic wafer-level packaging development for RF MEMS switch

Ferrandon

Greco

Lagoutte

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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This paper presents a low temperature «350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements:• Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance • Electrical connection between both wafers • Hermetic sealing under controlled atmosphere with 5 +1-0.5 /lm gap between the switch and the cap wafers • No degradation of the switch performances • Low temperature «350°C) packaging process to preserve the moving part materials • Electrode and dielectric for electrostatic hold • No sticking of the moving contact Two main processes were developed and implemented together: Au-Sn eutectic bonding under atmospheric pressure with 5/lm spacers to ensure the gap, and 'post-bonding' TSV. The complete process flow of the cap wafer, bonding and TSV process is presented. The solder material, made of 80wt.%Au and 20wt.%Sn, is only 5/lm thick and is electroplated. SEM, XPS, EDX analyses and shear tests have been performed. Hermeticity evaluation tests have been set-up, and a standard leak rate lower than 1.2 x 10-1 2 mbar.lls has been demonstrated using the membrane de flexion method. TSV and Au-Sn bump resistance is less than I4mn and IOmn with a yield of 92% and 98% respectively across the 200mm wafer. The resistance between 2 via is more than 500Mn at 5V. As to the packaged switch, its insertion losses at 2 GHz are 0.74dB and its off-state isolation is 43.6dB. At last, it has been demonstrated that the substrates resistivity has a great influence on the insertion losses. IntroductionTargeting the mobile communication market, a RF MEMS piezoelectric switch connecting upwards with low-voltage actuation and electrostatic hold has been developed [1] (Figure 1). Indeed, RF MEMS switches compared to semiconductor switches are known for their potential great performances at the GHz frequency range such as lower insertion losses, better isolation and better cut-off frequency.Piezoelectric actuation is a good means to have low operation voltage, and electrostatic hold enables strong pressure on the contact, producing low contact resistance and low RF losses. PZT has been selected for its high piezoelectric constants. Requiring a 5/lm gap enables

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“…Au-Sn provides a cost-friendly solution for SLID bonding when compared to Au-In material system. Au-Sn is a widely used material system for electronic packaging for both discrete device packaging and wafer-level packaging [17]- [20]. While the Sn enables a relatively lowtemperature bonding, IMCs of the Au-Sn material system provides mechanically reliable and robust bond [21]- [23].…”

Section: Introductionmentioning

confidence: 99%

Wafer-Level Low-Temperature Solid-Liquid Inter-Diffusion Bonding With Thin Au-Sn Layers for MEMS Encapsulation

Temel

Kalay

Akın

2021

J. Microelectromech. Syst.

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A novel solid-liquid inter-diffusion (SLID) bonding process is developed allowing to use thin layers of the Au-Sn material in wafer-level microelectromechanical systems (MEMS) packaging while providing a good bonding strength. The bond material layers are designed to have a robust bond material configuration and a metallic bond with a high re-melting temperature, which is an important advantage of SLID bonding or with its alternative name, transient liquid phase (TLP) bonding. The liquid phase in SLID bonding is the gold-rich eutectic liquid of the Au-Sn material system, where the bonding temperature is selected to be 320 • C for a reliable bonding. The average shear strength of the bonds is measured to be 38±1.8 MPa. The hermeticity of the package is tested with the He-Leak test according to MIL-STD 883, which yields a leak value lower than 0.1 × 10 −9 at m.cm 3 /s. The vacuum inside the package without a getter is calculated as 2.5 mbar after cap wafer thinning. The vacuum level is well preserved after post-processes such as annealing at 400 • C and the dicing process. These results verify that thin layers of Au-Sn materials can be used reliably with the SLID or TLP bonding technique using the new approach proposed in this study.

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A fluxless bonding process using AuSn or Indium for a miniaturized hermetic package

Cited by 11 publications

References 6 publications

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging

Hermetic wafer-level packaging development for RF MEMS switch

Wafer-Level Low-Temperature Solid-Liquid Inter-Diffusion Bonding With Thin Au-Sn Layers for MEMS Encapsulation

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