A floating point pipeline CORDIC processor with extended operation set

Abstract

In this paper a novel architecture of a DSP floating point, pipelined processor is presented which is based on the CORDIC and CCM algorithms. It provides for the Fist time a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications e.g. real time digital signal processing and matrix equation solving problems.

50 Years of CORDIC: Algorithms, Architectures, and Applications

“…The earliest pipelined architecture that we find was suggested by Deprettere, Dewilde and Udo in 1984 [14]. Pipelined CORDIC circuits have been used thereafter for high-throughput implementation of sinusoidal wave generation, fixed and adaptive filters, discrete orthogonal transforms and other signal processing applications [40]- [44]. A generic architecture of pipelined CORDIC circuit is shown in Fig.…”

Coordinate Rotation Digital Computer Algorithm: Design and Architectures

“…The earliest pipelined architecture that we find was suggested in 1984. Pipelined CORDIC circuits have been used thereafter for highthroughput implementation of sinusoidal wave generation, fixed and adaptive filters, discrete orthogonal transforms and other signal processing applications [8].…”

A floating-point advanced cordic processor

“…This is achieved by modifying the CORDIC and CCM algorithm, so that they can be mapped into the same pipe segments. The implementation of the two algorithms in a common architecture is partly studied in [18][19] by the authors.…”