A Flexible Profiling Sub-System for Reconfigurable Logic Architectures

Valente, G.; Muttillo, Vittoriano; Pomante, Luigi; Federici, Fabio; Faccio, Marco; Moro, A.; Ferri, S.; Tieri, Carlo

doi:10.1109/pdp.2016.86

Cited by 16 publications

(13 citation statements)

References 8 publications

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“…This is important for systems with real-time requirements. The complete monitoring system can be implemented using a library of elements, called AIPHS ( [30,31]). In particular, AIPHS is composed of hardware monitoring units, called sniffers (S), connected to a Global Monitor unit (GM): GM interfaces with sniffers in order to initialize and collect their information.…”

Section: Monitoring Systemmentioning

confidence: 99%

“…In the case of SPOF, the Global monitor is represented by the Nios II processor. The metrics can be of different types: in SPOF, accepted metrics are (i) memory exploitation metrics, (ii) HW communication metrics (iii) overall execution time metrics and (iv) code coverage metrics [30]. With these metrics, the sniffer generation is automatic.…”

Section: Monitoring Systemmentioning

confidence: 99%

See 1 more Smart Citation

SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

Valente

Muttillo

et al. 2019

Energies

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We here present a new PLC-POWERLINK industrial solution for Industry 4.0 applications. The proposed solution provides the capability to separate the sensing functionality from the PLC-side, in demand for the reconfigurable FPGA implementation. In particular, we here provide a framework that supports the interfacing between the POWERLINK protocol and commonly used standards, such as I2C, SPI, and UART. This has been obtained by using a framework built around a soft IP-core Application Processor, which manages the interfacing with several POWERLINK slaves, able to support the data exchange with the POWERLINK Communication Processor. A practical application example and related implementation details are presented in the paper.

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Section: Monitoring Systemmentioning

confidence: 99%

Section: Monitoring Systemmentioning

confidence: 99%

SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

Valente

Muttillo

et al. 2019

Energies

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show abstract

“…In order to avoid as much as possible introducing overhead in the software execution, the proposed flow is based on a hardware solution. In fact, it exploits a fully customizable and portable distributed HW solution based on the library called AIPHS ( [25,26]): specifically, it is a library of elements to be used to realize a monitoring solution. In fact, it allows to consider architectures based on different soft-processors while changing only few hardware components.…”

Section: Monitoring Systemmentioning

confidence: 99%

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

et al. 2016

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In recent years, the use of multiprocessor systems has become increasingly common. Even in the embedded domain, the development of platforms based on multiprocessor systems or the porting of legacy single-core applications are frequent needs. However, such designs are often complicated, as embedded systems are characterized by numerous non-functional requirements and a tight hardware/software integration. This work proposes a methodology for the development and validation of an embedded multiprocessor system. Specifically, the proposed method assumes the use of a portable, open source API to support the parallelization and the possibility of prototyping the system on a field-programmable gate array. On this basis, the proposed flow allows an early exploration of the hardware configuration space, a preliminary estimate of performance, and the rapid development of a system able to satisfy the design specifications. An accurate assessment of the actual performance of the system is then enforced by the use of an hardware-based profiling subsystem. The proposed design flow is described, and a version specifically designed for LEON3 processor is presented and validated. The application of the proposed methodology in a real case of industrial study is then presented and analyzed.

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“…Many academic and industrial solutions are available in literature to address these issues. The works in [5], [6], [7], [3], and [8] all offer a solution to compose a monitoring system in a modular way, starting from the basic events to be monitored and building the monitor to capture and store them. Works in [9] and [10] both allow to design and introduce a monitoring system during a High-Level Synthesis (HLS) flow.…”

mentioning

confidence: 99%

“…However, both the approaches based on HLS and data-mining provide monitors difficult to combine with SW-tasks, due to a monitor creation that does not take into account microprocessors architectures, limiting their flexibility. Modular monitoring solutions represent a promising approach, but the available ones lack in applicability to different RQMs, being typically focused on specific purposes, i.e., debugging [5], or timing performance [3], [6]. Only the work in [8] targets both performance-and debugging-oriented monitoring over heterogeneous architectures.…”

mentioning

confidence: 99%

Non-Intrusive In-Situ Requirements Monitoring of Embedded System

Seo

Lysecky

2018

ACM Trans. Des. Autom. Electron. Syst.

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Accounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. Monitoring and verifying system requirements at runtime enable a system to continuously and introspectively ensure the system is operating correctly in the presence of dynamic execution scenarios. In this article, we present a requirements-driven methodology enabling efficient runtime monitoring of embedded systems. The proposed approach extracts a runtime monitoring graph from system requirements specified using UML sequence diagrams. Non-intrusive, on-chip hardware dynamically monitors the system execution, verifies the execution adheres to the requirements model, and in the event of a failure provides detailed information that can be analyzed to determine the root cause. Using case studies of an autonomous vehicle and pacemaker prototypes, we analyze the relationship between event coverage, detection rate, and hardware requirements

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A Flexible Profiling Sub-System for Reconfigurable Logic Architectures

Cited by 16 publications

References 8 publications

SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

Non-Intrusive In-Situ Requirements Monitoring of Embedded System

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