2008
DOI: 10.1063/1.3046115
|View full text |Cite
|
Sign up to set email alerts
|

A flexible organic pentacene nonvolatile memory based on high-κ dielectric layers

Abstract: We report a pentacene thin film transistor nonvolatile memory fabricated on a flexible polyimide substrate. This device shows a low program/erase voltage of 12 V, a speed of 1/100 ms, an initial memory window of 2.4 V, and a 0.78 V memory window after 48 h. This has been achieved by using a high-dielectric as charge trapping, blocking, and tunneling gate insulator layers.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

1
32
0

Year Published

2010
2010
2023
2023

Publication Types

Select...
8

Relationship

1
7

Authors

Journals

citations
Cited by 48 publications
(33 citation statements)
references
References 16 publications
1
32
0
Order By: Relevance
“…We used bottom-gate IGZO TFT NVM devices [7], [8]. A 500-nm wet oxide was grown on a 4-in Si wafer to mimic the glasslike insulator substrate [9].…”
Section: Methodsmentioning
confidence: 99%
See 2 more Smart Citations
“…We used bottom-gate IGZO TFT NVM devices [7], [8]. A 500-nm wet oxide was grown on a 4-in Si wafer to mimic the glasslike insulator substrate [9].…”
Section: Methodsmentioning
confidence: 99%
“…An erase saturation that is due to trap-assisted gate leakage was found. However, this is inevitable even for high-temperature-formed high-κ blocking oxide [5], [6] and becomes worse at lower temperature [7]. During erase, the trapped electrons need to be removed over the tunnel oxide to lower V t ; alternatively, the minority holes in the depleted IGZO can tunnel into the trapping layer and annihilate the trapped electrons.…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…A solution to lower the program and erase voltages is to use high-k dielectrics. Chang et al fabricated an OFET memory device containing HfLaO (20 nm), HfON (20 nm), and HfO 2 (6 nm) as blocking, charge trapping, and tunneling gate insulator layers, respectively [26]. The devices showed a low program/erase voltage of 12 V, a speed of 1/100 ms, an initial memory window of 2.4 V, and a 0.78 V memory window after 48 hours.…”
Section: Floating Gate Ofet Memorymentioning
confidence: 99%
“…18,19 It has been reported that TOMDs have memory functions from ferroelectric polymers, metal nanoparticles or charge trapping layers, and polymer energy well structures. [20][21][22][23][24][25][26][27][28][29][30] However, most TOMDs reported to date have limitations with respect to high operation voltages and/or poor retention (stability) characteristics, even though basic memory functions in transistor structures can be welldemonstrated. Thus, it is very important to achieve both low voltage and high retention characteristics at the same time for further consideration toward commercialization of TOMDs, particularly for mobile applications, of which the first priority is low power consumption, as well as stability.…”
Section: Introductionmentioning
confidence: 99%