A flexible LDPC decoder architecture supporting two decoding algorithms

Huang, Shuangqu; Bao, Dan; Xiang, Bo; Chen, Yun; Zeng, Xiaoyang

doi:10.1109/iscas.2010.5537686

Cited by 12 publications

(6 citation statements)

References 7 publications

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“…It computes the MSA algorithm and explores the TPMP decoding schedule [4]. The LDPC core integrates two parallel datapaths in the same core: i) for CN processing Eq.…”

Section: Decoding Architectures a Ldpc Core Architecturementioning

confidence: 99%

“…The engine is associated with a dedicated input stream for γ messages and with one output stream forα messages (2) or the hard-decoded bit states (4).…”

Section: A Ldpc Dataflow Enginementioning

confidence: 99%

“…Thus, c is a codeword from the set C if it verifies the condition c × H T = 0, c ∈ C, where H is the parity-check matrix of the code and C is the null-space of H. Alternatively, H can be seen as the adjacency matrix of the code's Tanner graph, a bipartite graph, as shown in Figure 1, where rows and columns define a node type and the non-null elements, i.e., the bits or Bit Nodes (BNs) participating in a parity-check equation or Check Node (CN), constitute the graph's edges. The following notation is associated with the LDPC codes: (N, K) are the code and information dimensions; edges (non-null elements in H) connect BNs to CNs; γ n a-priori reliability (LLR) of BN n ; α nm message sent from BN n to CN m ; β mn message sent from CN m to BN n ;α n a-posteriori LLR of BN n; M (n)/N (m) set of CNs/BNs adjacent to BN n /CN m ; Decoding algorithms are inherently parallel, as nodes of each kind, BNs and CNs, can be processed in parallel, in two decoding phases [4], known as flooding decoding schedule or Two-Phased Message Passing (TPMP). Among the LDPC decoding algorithms, the Min-Sum Algorithm (MSA) is a very popular one due to the arithmetic nature of the operations carried out [5].…”

Section: Introductionmentioning

confidence: 99%

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Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

Andrade

Pratas

Falcão

et al. 2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Power and flexibility are important constraints in the design of new chips. The efficiency extracted from a design is increasingly becoming a dominant question, and several techniques and technological advances can be used to optimize efficiency in its energy and functionality domains. These two characteristics are critical in digital communication systems that must work accordingly with multiple communication standards at different power, throughput and latency requirements. In this work, we focus on the physical layer Forward Error Correcting (FEC) system, due to the tight throughput and latency constraints they are required to meet, and develop specialized processing engines for Low-Density Parity-Check (LDPC) codes decoding, a class of widely standardized codes. The engines were developed for execution on Field-Programmable Gate Array (FPGA) devices by exploring dataflow and widepipeline design approaches, and have the design flexibility to target different LDPC codes, since they were implemented using recent High-Level Synthesis (HLS) tools. The generated engines and architectures allow achieving highly efficient decoders with decoding throughputs ranging from 16 Mbit/s to 1.2 Gbit/s at energy efficiencies of 42 to 908 Mbit/Joule/iteration, while the achieved clock frequencies of operation vary from 80 to 300 MHz. Furthermore, our bandwidth analysis shows that workload boundaries do not impose limitations on a system bus.

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“…It computes the MSA algorithm and explores the TPMP decoding schedule [4]. The LDPC core integrates two parallel datapaths in the same core: i) for CN processing Eq.…”

Section: Decoding Architectures a Ldpc Core Architecturementioning

confidence: 99%

“…The engine is associated with a dedicated input stream for γ messages and with one output stream forα messages (2) or the hard-decoded bit states (4).…”

Section: A Ldpc Dataflow Enginementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

Andrade

Pratas

Falcão

et al. 2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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show abstract

“…Considering a decoder parallelism P = z, as in state-of-the-art layered decoders, one sub matrix (equal to P edges) is processed per clock cycle, with one operation completed by each PE working in a serial fashion. In [33], the intrastandard flexibility comes together with a choice among two decoding approaches, the layered decoding and the TPMP. Although this ASIC performance has been evaluated only in case of the structured QC-LDPC codes of WiMAX, the true benefit from the dual algorithm comes in case of unstructured codes.…”

Section: Serial Pementioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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“…The 2-bit SM indicates the sign (i.e., positive or negative) and the type of minimum (i.e., min0 or min1). The basic concept for storing the CN messages in a compressed way is similar to the method in [17][18][19], but our CN memory structure and implementation are different from them. Since CN memory does not store all the min0s, we need to restore the 2's complement value of each CN message using the Mag_min0s, Mag_min1s and SM information stored in the CN memory.…”

Section: Check Node Memorymentioning

confidence: 99%

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Shin¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-m CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V

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A flexible LDPC decoder architecture supporting two decoding algorithms

Cited by 12 publications

References 7 publications

Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

Flexible LDPC Decoder Architectures

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

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