A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format

“…The horizontal dotted lines represent the FEC thresholds of three common FEC codes used in datacenter applications: BCH(3456,3084), RS(528,514) and RS(280,260) [12]. The accuracy used in both cases was set to (10,8) while 16 taps were employed for the 56 Gb/s NRZ signal and 32 taps for the 40 GBaud PAM-4. The improvement Fig.…”

“…Recently we demonstrated a high-performance FPGA implementation of an FFE for optical interconnects and verified its performance with an externally modulated link operating up to 40 Gb/s [8]. In this paper we demonstrate dynamic reconfiguration of the FFE, and its successful operation with varying modulation format (NRZ, PAM-4), baudrate (ranging from 32-56 Gbaud) and transmission reach (0-2 km), achieving maximum throughput up to 80 Gb/s and sampling rate up to 56 GSa/s.…”

Design methodologies, frameworks and implementations on reconfigurable devices for timing and energy optimizations

“…Contrary to the past, FPGAs have expanded their usage of "prototype-only", or "connectivity-only" to a high-performance tool which is able to deliver tremendous performance per Watt [41,78,42]. The most prominent characteristics of FPGAs are: i) their inherent parallel architecture which enables the deployment of highly parallel designs with impressive throughput rates [104,66,161], ii) the low operation frequency which allows for reduced power consumption, and iii) the reconfiguration/reprogramability which provides increased flexibility and reusability of the chip for a broad range of applications and operations [103,53,33]. The aforementioned capabilities promote FPGAs as a promising solution to the ever-growing performance per Watt demands of datacenter and embedded applications [60,78].…”

“…We describe parallelization techniques to accelerate FFE, accuracy analysis for various FFE scenarios, as well as a design space exploration leading to fine-tuned and platform-dependent FFE customization. We clarify that this work [104] is a product of a group of people, with the thesis author's contributions being on the HW architecture design, parallelization techniques and DSE trade-off analysis between throughput and accuracy relating to the FPGA implementation.…”

“…For presentation purposes, we briefly describe the setup performed by PCRL, while in-depth details can be found in [104]. To investigate the performance of the implemented digital equalizer, a typical optical interconnect was implemented with the experimental setup of Fig.…”