A flexible design flow for software IP binding in commodity FPGA

Gora, Michael; Maiti, Abhranil; Schaumont, Patrick

doi:10.1109/sies.2009.5196217

Cited by 9 publications

(2 citation statements)

References 32 publications

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“…Gora et al in [36] present an alternative way for protecting SW-IP in FPGAs by binding it to a hardware platform using a PUF in the FPGA's reconfigurable logic. Their proposed method specifically protects software and assumes that the hardware soft IP cores are securely configured by other means of protection.…”

Section: B Academic Researchmentioning

confidence: 99%

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Maes

Schellekens

Verbauwhede

2012

IEEE Trans.Inform.Forensic Secur.

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Abstract-Currently achievable intellectual property (IP) protection solutions for field-programmable gate arrays (FPGAs) are limited to single large "monolithic" configurations. However, the ever growing capabilities of FPGAs and the consequential increasing complexity of their designs ask for a modular development model, where individual IP cores from multiple parties are integrated into a larger system. To enable such a model, the availability of IP protection at the modular level is imperative. In this work, we propose an IP protection mechanism for FPGA designs at the level of individual IP cores, by making use of the self-reconfiguring capabilities of modern FPGAs and deploying a trusted third party to run a metering service, similar to the work of Güneysu et al. and Drimer et al. The proposed scheme makes it possible to enforce a pay-per-use licensing scheme which holds considerable advantages, both for IP core providers as well as for system integrators. Moreover, the scheme has a minimal implementation overhead and is the first of its kind to be solely based on primitives that are already available in recent commercially available FPGA devices. This allows for an immediate and feasible deployment, in contrast to earlier proposed solutions.Index Terms-Cloning, design security, field-programmable gate array (FPGA), hardware metering, intellectual property (IP) protection, reverse-engineering, soft intellectual property (IP).

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Section: B Academic Researchmentioning

confidence: 99%

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Maes

Schellekens

Verbauwhede

2012

IEEE Trans.Inform.Forensic Secur.

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“…To ensure the legality of IP core and make it use in a licensed device, Gora et al [18] extracted 128 bit secret key by a PUF in FPGA and used it to encrypt software IP core. Therefore, an IP core is binding to a specific FPGA device.…”

Section: Related Workmentioning

confidence: 99%

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

Long

Liang

et al. 2019

IEEE Access

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With rapid advances in edge computing and the Internet of Things, the security of low-layer hardware devices attract more and more attention. As an ideal hardware solution, field programmable gate array (FPGA) becomes a mainstream technology to design a complex system. The designed modules are named as intellectual property (IP) cores. In this paper, we consider both misappropriation of hardware devices and software IPs in edge computing and propose a PUF-based IP copyright anonymous authentication scheme. The scheme utilizes the double physical unclonable function (PUF) authentication model. Both the parties generate the challenge jointly in authentication to avoid replay attack and modeling attack on PUF circuit. The complexity of authentication is greatly reduced. Besides, the server of FPGA vendor is unnecessary to store all the challenge response pairs (CRPs) of each PUF-based chip due to the use of the double PUF authentication model. It saves the system resource and achieves better security. To protect software IP, IP core vendor inserts copyright information and anonymous buyer identity information into the design before trading. The anonymity of the buyer ensures the benefits of the buyer. With the participation of trustable device vendor, infringement behavior can be traced according to extracted fingerprints. The experiments show that the resource overhead of the proposed scheme is reduced by 61.96% and 31.61% by comparing with 2-1 DAPUF and built-in self-adjustable PUF. Besides, PUF stability is 99.54%. It demonstrates the good performance of the proposed scheme. INDEX TERMS Edge computing, field programmable gate array (FPGA), IP cores, PUF authentication model, anonymous authentication.

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