A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing

Abstract

proposed adder is utilized in some image processing Abstract-A fixed delay split adder is presented. The adder applications and results are shown in Section IV. Finally breaks the total addition into sum and reminder with an expected some concluding remakes are noted.reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of II. LITERATURE REVIEW the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close Although the idea of using approximate addition has not matching to the perfect cases when ignoring the reminder.been suggested in literature, it is rather beneficial to discuss some of the existing architectures, particularly in terms of Index Terms-approximate addition, binary adders, computer delay and gate count: The well known Ripple adder is formed arithmetic, high-speed adders, image processing. by cascading n full adders for an n-bit addition operation [1].The adder complexity is 6n gates, which is the least among all I. INTRODUCTION other adders; however, its delay to produce all sum bits is the I ae a b d s c r s y worst since the last carry signal must wait 2n gate delay times. the addersthae beny disc ss oprensivl in Logarithmic time parallel adders are considered the fastest the pen iterturefor anyyear. Deendig onthe and can be categorized into two classes: carry look-ahead and desired application, criteria such as speed, power, and aconditional-sum algorithms [4]. The carrylook-ahead adder hardware complexity (gate count or silicon area) are employed computes, typc ally,ifour bit.aT e in lonebo and in choosing the optimum architecture. When area is an issue, op tes the fifth carry to the next stage. For a 16-bt adder sequential adders of small block sizes are preferred over the propaga parallel architectures where the carry signals are computed all for example, the delay is only 8 gate delays (instead of 32 for at once. Most of the other existing architectures for binary the ripple adder) trading more hardware complexity.An even faster architecture is the carry select adder, where addition, in general, lay between these two extremes.it baial dulcae th stgswt.oehvn '0'cryi For applications of high computational complexities and and the other having '1' in order to prepare the output faster.high speed processing necessities, fast and yet small sized The output signals are then multplexed based on the actual adders are desirable. Fortunately, some of these applications do not require perfect outcomes, especially when dealing with carry of each stage. This algorithm saves one gate delay for noise, filtering or human hearing or vision. every 4-bit block trading of course hardware complexity.