2015
DOI: 10.1145/2778970
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A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching

Abstract: Timing characterization of standard cells is one of the essential steps in VLSI design. The traditional static timing analysis (STA) tool assumes single input switching models for the characterization of multiple input gates. However, due to technology scaling, increasing operating frequency, and process variation, the probability of the occurrence of multiple input switching (MIS) is increasing. On the other hand, considering all possible MIS scenarios for the characterization of multiple input logic gates, i… Show more

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Cited by 7 publications
(3 citation statements)
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“…Note that δ ↓ S (−∞) = δ ↓ S (∞) is mainly caused by transistor T 2 , which is closed in one case, connecting nodes N and O, while in the other it is open (see Section III). Although the absolute values differ, our results fit very well 2 to previous investigations in other technologies [7], [8], [9].…”
Section: Multiple Input Switching (Mis)supporting
confidence: 91%
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“…Note that δ ↓ S (−∞) = δ ↓ S (∞) is mainly caused by transistor T 2 , which is closed in one case, connecting nodes N and O, while in the other it is open (see Section III). Although the absolute values differ, our results fit very well 2 to previous investigations in other technologies [7], [8], [9].…”
Section: Multiple Input Switching (Mis)supporting
confidence: 91%
“…A less visible phenomenon of the speed-up MIS effect deserve to be mentioned here: Simulations for an older 65 nm technology and results reported in the literature (e.g. in [7], [8]) reveal local delay maxima for medium-sized |∆|. We conjecture these to be caused by input-output coupling capacitances, which introduce a current working against the intended behavior of the gate.…”
Section: Multiple Input Switching (Mis)mentioning
confidence: 63%
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