2015 IEEE Computer Society Annual Symposium on VLSI 2015
DOI: 10.1109/isvlsi.2015.113
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A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies

Abstract: Contemporary digitally controlled delay elements trade off power overheads and delay quantization error. This paper proposes a new delay element that provides a balanced design that yields low power with low delay quantization error. The proposed element has a quasi linear delay characteristic, with uniform delay differences between adjacent codewords. The element employs and leverages the advantages offered by a 28nm FD-SOI technology, using its back body biasing feature to add an extra dimension to its progr… Show more

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Cited by 8 publications
(21 citation statements)
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References 18 publications
(43 reference statements)
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“…DLs have three interesting properties that simplify delay analysis: (1) the nets do not have glitches, (2) the time windows of the nets do not overlap, and (3) all nets have single fanout 4 . In this way, simple delay models can be used and crosstalk can be ignored by simply isolating or shielding the DL.…”
Section: A Gate and Wire Delay Modelsmentioning
confidence: 99%
See 4 more Smart Citations
“…DLs have three interesting properties that simplify delay analysis: (1) the nets do not have glitches, (2) the time windows of the nets do not overlap, and (3) all nets have single fanout 4 . In this way, simple delay models can be used and crosstalk can be ignored by simply isolating or shielding the DL.…”
Section: A Gate and Wire Delay Modelsmentioning
confidence: 99%
“…• All the wires must have the same width. 4 Property (3) is not fully complied when synthesizing configurable DLs with muxes (see section V). • Large spacing rules between wires are defined.…”
Section: A Gate and Wire Delay Modelsmentioning
confidence: 99%
See 3 more Smart Citations