A fine‐grained thread‐aware management policy for shared caches

Cache partitioning is a successful technique for saving energy for a shared cache and all the existing studies focus on multi-program workloads running in multicore systems. In this paper, we are motivated by the fact that a multi-thread application generally executes faster than its single-thread counterpart and its cache accessing behavior is quite different. Based on this observation, we study applications running in multi-thread mode and classify data of the multi-thread applications into shared and private categories, which helps reduce the interferences among shared and private data and contributes to constructing a more efficient cache partitioning scheme. We also propose a hardware structure to support these operations. Then, an access adaptive and thread-aware cache partitioning (ATCP) scheme is proposed, which assigns separate cache portions to shared and private data to avoid the evictions caused by the conflicts from the data of different categories in the shared cache. The proposed ATCP achieves a lower energy consumption, meanwhile improving the performance of applications compared with the least recently used (LRU) managed, core-based evenly partitioning (EVEN) and utility-based cache partitioning (UCP) schemes. The experimental results show that ATCP can achieve 29.6% and 19.9% average energy savings compared with LRU and UCP schemes in a quad-core system. Moreover, the average speedup of multi-thread ATCP with respect to single-thread LRU is at 1.89.

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“…The constraints are the same with those in the two-stage model, that is, constraints (12), (13), (14), (15) and (16).…”

Section: Comparison With One-stage Methodsmentioning

confidence: 99%

“…Promotion policy determines how to update the hit cache line in the replacement priority order. The thread-aware Dynamic Insertion Policy (TADIP) [15][16][17] dynamically chooses the insertion policies of the traditional LRU policy and the Bimodal Insertion Policy, according to the cache requirements of different applications.…”

Section: Introductionmentioning

confidence: 99%

Access Adaptive and Thread-Aware Cache Partitioning in Multicore Systems

et al. 2018

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“…Two of the main sources of inefficiency in current caches are the nonuniform distribution of the memory accesses across the cache sets, which causes misses because of the mapping restrictions of non fully associative caches and the access patterns with little locality that degrade the performance of caches under the traditional least recently used replacement policy. This special issue finishes with a paper by Rolán et al [3] that proposes a technique to tackle in a coordinated way both kinds of problems in the context of chip multiprocessors, whose last-level caches can be shared by threads with different patterns of locality. This proposal, called thread-aware mapping and replacement miss reduction (TAMR2) policy, tracks the behavior of each thread in each set in order to decide the appropriate combination of policies to deal with these problems.…”

mentioning

confidence: 99%

“…This special issue finishes with a paper by Rolán et al . that proposes a technique to tackle in a coordinated way both kinds of problems in the context of chip multiprocessors, whose last‐level caches can be shared by threads with different patterns of locality. This proposal, called thread‐aware mapping and replacement miss reduction (TAMR2) policy, tracks the behavior of each thread in each set in order to decide the appropriate combination of policies to deal with these problems.…”

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confidence: 99%

Multicore cache hierarchies: design and programmability issues

Doallo

Plata

2013

Concurrency and Computation

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Welcome to this special issue of the journal Concurrency and Computation: Practice and Experience on Multicore Cache Hierachies -Design and Programmability Issues, which contains three original manuscripts. Caches have been playing an essential role in the performance of single-core systems due to the gap between processor speed and main memory latency. First level caches are strongly restricted by their access time but current processors are able to hide most of their latency using outof-order execution as well as miss overlapping techniques. On the other hand, last levels of the cache memory hierarchy are not so dependable on their access time but on their locality issues. The locality in lower levels is filtered by the upper levels. As requests going down in the memory hierarchy, they require a greater number of cycles to be satisfied, so it becomes more difficult to hide the latency of last-level caches. In multicore systems, their importance is even larger due to the growing number of cores that share the bandwidth that this memory can provide. In an attempt to make a more efficient usage of their caches, the memory hierarchies of many chip multiprocessors present last-level caches, which can be allocated across threads and part of them may be private to a thread while other parts may be shared by multiple threads. Then, caching techniques will continue their evolution during next years in order to tackle the new challenges imposed by multicore platforms and workloads. A clear indicator of the current interest of the research community in new techniques for optimizing the performance and power consumption of multicore cache hierarchies is the organization during last years of specific sessions devoted to these topics at top international conferences on computer architecture and parallel computing.This special issue contributes to this promising field with extended and carefully reviewed versions of selected papers first from the International Workshop on Multicore Cache Hierachies -Design and Programmability Issues, which was held as part of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2012) in Madrid (Spain), and second from all the community in the field as the Call for Papers was also open to contributions that were not sent to the mentioned workshop.The first contribution, by O. G. Lorenzo et al.[1], presents a set of three hardware counter (HC)-based tools to characterize memory access of parallel codes in symmetric multiprocessors. This toolkit simplifies accessing and programming HCs, which are included in modern microprocessors. Hardware counters are used to obtain information about memory accesses in a parallel code at very low cost. This information is presented to the user in a friendly way. The first tool can be used to automatically monitor the memory accesses of a system and to analyze a code even if the source is not available. The second tool allows the user to insert in a source code, in a simple and transparent way, the instructions n...

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