A Fault-Tolerant Modular Architecture for Binary Trees

Hassan, Mahmudul; Agarwal,

doi:10.1109/tc.1986.1676770

Cited by 57 publications

(1 citation statement)

References 8 publications

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“…There are a few of papers on the Tree-structured system. Research on the reliability of trees can be found in topics such as fault-tolerance design of binary trees [2][3][4], and the reliability of fault-tolerant systems [5]. Kershenbaum&Slyke [6] presented a general algorithm for analyzing trees.…”

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation for Binary Directed Tree-Structured Systems Based on Terminal Failure Limit-Value

Chen

Liu

2011

AMM

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This paper evaluates reliability of binary directed tree-structured systems based on terminal failure limit-value. For the difficult problem with complex structures and directed transitive relation, the paper describes nodes in the tree system using set algebra, and uses set operations to compute a combinational mode of failed nodes, and then describes it with family of sets. On that basis, an effective algorithm is shown, and a numerical example is given to illustrate the algorithm obtained in the paper.

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Section: Introductionmentioning

confidence: 99%

Reliability Evaluation for Binary Directed Tree-Structured Systems Based on Terminal Failure Limit-Value

Chen

Liu

2011

AMM

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Reliability analysis of tree‐based networks and its application to fault‐tolerant VLSI systems

Roccetti

1995

Networks

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A probabilistic model is proposed that allows one to solve stochastic network reliability problems for treetype networks of N nodes, taking O( log N) time. The considered networks are based on interconnection patterns consisting of complete binary trees in which spare edges are added according to different criteria.We show that the use of this probabilistic model allows one to evaluate, taking O(l0g N ) time, the average connectedness (i.e., the expected number of processing elements still functioning in the presence of random faults) of dynamically reconfigurable fault-tolerant VLSl systems which are based on such tree-based structures. Finally, numerical results obtained from the model are provided that show that, given a fixed chip silicon area, several of the analyzed VLSl architectures have a notably greater expected number of working processing elements w.r.t. complete binary trees, in the presence of a given fault distribution. 0 7995 John Wiley & Sons, Inc.

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