A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model

Zhang, Jian; Wang, Ran; Pei, Xudong; Luo, Dan; Hussain, Sajjad; Zhang, Guohe

doi:10.1109/tcsii.2021.3137987

Cited by 8 publications

(5 citation statements)

References 19 publications

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“…A genetic algorithm for adjusting the membrane threshold of neurons is proposed to improve the image processing quality. The authors of [101] implemented an SNN accelerator with reduced latency based on timing of pulses with data reuse. Paper [102] analyzed the backpropagation algorithm problems for SNN training.…”

Section: A Spiking Neural Networkmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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The technology development greatly increases the amount of digital visual information. Existing devices cannot efficiently process such huge amounts of data. The technical characteristics of digital image processing (DIP) devices and systems are being actively improved to resolve this contradiction in science and technology. The state-of-the-art methodology includes a huge number of very diverse approaches at the mathematical, software, and hardware implementation levels. We have analyzed all modern trends to improve the technical characteristics of DIP devices and systems. The main distinguishing feature of this review is that we are not limited to considering various aspects of neural network image processing, to which the vast majority of both review and research papers on the designated topic are devoted. Review papers on the subject under consideration are analyzed. Various mathematical and arithmetic-logical methods for improving the characteristics of image processing devices are described in detail. Original and significant architectural and structural solutions are analyzed. Promising neural network models of visual data processing are characterized. Hardware platforms for the design and operation of DIP systems that are efficient in terms of resource costs are considered. The most significant improvements achieved through the hardware implementation of models and methods on field-programmable gate arrays and application-specific integrated circuits are noted.INDEX TERMS High-performance computing, low-area design, low-power device, energy-efficient architecture, neural network, hardware accelerator, FPGA, ASIC.

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Section: A Spiking Neural Networkmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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show abstract

“…Using this algorithm, they obtained values for learning through repetitive calculations of complex expressions represented by SNN as exponential functions. Another group used a back-propagation STDP (BP-STDP) algorithm and a weighted neuron model [28]. The proposed accelerator is implemented in the Xilinx Virtex-7 VC707 FPGA development board and achieves better accuracy due to the efficient and supervised BP-STDP rule.…”

Section: ) Required Memory Sizementioning

confidence: 99%

A Digital Processing in Memory Architecture Using TCAM for Rapid Learning and Inference Based on a Spike Location Dependent Plasticity

Kim

Choi

et al. 2023

IEEE Access

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In this paper, we present a digital processing in memory (DPIM) configured as a stride edgedetection search frequency neural network (SE-SFNN) which is trained through a spike-location-dependent -plasticity (SLDP), a learning mechanism reminiscent of spike-timing-dependent plasticity. This mechanism allows for rapid online learning as well as a simple memory-based implementation. In particular, we employ a ternary data scheme to take advantage of a ternary content addressable memory (TCAM). The scheme utilizes a ternary representation of the image pixels and the TCAMs are used in a two-layer format to significantly reduce the computation time. The first layer applies several filtering kernels followed by the second layer that reorders pattern dictionaries of TCAMs to place the most frequent patterns at the top of each supervised TCAM dictionary. Numerous TCAM blocks in both layers operate in a massively parallel fashion using digital ternary values. There are no complicated multiply operations performed and learning is performed in a feedforward scheme. This allows rapid robust learning as a trade-off with the parallel memory block size. Furthermore, we propose a method to reduce the TCAM memory size using a two-tiered minor to major promotion (M2MP) of frequently occurring patterns. This reduction scheme is performed concurrently during the learning operation without incurring a preconditioning overhead. We show that with a minimal circuit overhead, the required memory size is reduced by 84.4% and the total clock cycles required for learning also decrease by 97.31 % while the accuracy decreases only by 1.12%. We classified images with 94.58% accuracy on the MNIST dataset. Using a 100MHz clock, our simulation results show that the MNIST training takes about 6.3 ms dissipating less than 4mW of average power. In terms of the inference speed, the trained hardware is capable of processing 5,882,352 images per second. INDEX TERMS Digital processing in memory, fast training, in memory computation, TCAM I. INTRODUCTIONRecently, various products using artificial intelligence algorithms have been released. Examples include home appliances such as refrigerators and air conditioners, automobiles for autonomous driving, and smart factories. These products collected data from edge devices and then sent the collected data to the server, where learning and computation were performed on the server [1]. However, in this case, there is a delay in the transmitting to the server and receiving the neural network weights. In addition, userspecific learning cannot be performed because it is not trained using only the data generated from the user's edge device. Due to these shortcomings, Artificial intelligence on things (AIoT) technology that can learn from edge devices was recently introduced [2].Unlike the existing convolutional neural networks (CNNs) and deep neural networks (DNNs) methods in which heavy amounts of iterative computation between tensors are

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“…Therefore, under the same hardware structure design methodology, the rate-based SNN accelerators have to access the memory at least 4× more than the temporal coding SNN accelerator. Zhang's work (Zhang et al, 2021) and Skydiver (Chen et al, 2022) are recent rate-based SNN accelerators that all suffer from low energy efficiency due to a large number of spikes. Shenjing (Wang et al, 2020) also has to process a large number of spikes due to its rate coding scheme, which harms the energy efficiency.…”

Section: Related Work Rate-based Snn Acceleratorsmentioning

confidence: 99%

A TTFS-based energy and utilization efficient neuromorphic CNN accelerator

Xiang

Srivatsa

et al. 2023

Front. Neurosci.

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Spiking neural networks (SNNs), which are a form of neuromorphic, brain-inspired AI, have the potential to be a power-efficient alternative to artificial neural networks (ANNs). Spikes that occur in SNN systems, also known as activations, tend to be extremely sparse, and low in number. This minimizes the number of data accesses typically needed for processing. In addition, SNN systems are typically designed to use addition operations which consume much less energy than the typical multiply and accumulate operations used in DNN systems. The vast majority of neuromorphic hardware designs support rate-based SNNs, where the information is encoded by spike rates. Generally, rate-based SNNs can be inefficient as a large number of spikes will be transmitted and processed during inference. One coding scheme that has the potential to improve efficiency is the time-to-first-spike (TTFS) coding, where the information isn't presented through the frequency of spikes, but instead through the relative spike arrival time. In TTFS-based SNNs, each neuron can only spike once during the entire inference process, and this results in high sparsity. The activation sparsity of TTFS-based SNNs is higher than rate-based SNNs, but TTFS-based SNNs have yet to achieve the same accuracy as rate-based SNNs. In this work, we propose two key improvements for TTFS-based SNN systems: (1) a novel optimization algorithm to improve the accuracy of TTFS-based SNNs and (2) a novel hardware accelerator for TTFS-based SNNs that uses a scalable and low-power design. Our work in TTFS coding and training improves the accuracy of TTFS-based SNNs to achieve state-of-the-art results on the MNIST and Fashion-MNIST datasets. Meanwhile, our work reduces the power consumption by at least 2.4×, 25.9×, and 38.4× over the state-of-the-art neuromorphic hardware on MNIST, Fashion-MNIST, and CIFAR10, respectively.

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A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model

Cited by 8 publications

References 19 publications

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

A Digital Processing in Memory Architecture Using TCAM for Rapid Learning and Inference Based on a Spike Location Dependent Plasticity

A TTFS-based energy and utilization efficient neuromorphic CNN accelerator

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