A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC

Cai, Yujie; Fan, Yibo; Huang, Leilei; Zeng, Xiaoyang; Yin, Haibing; Zenga, Bing

doi:10.1109/tcsvt.2021.3093579

Cited by 5 publications

(5 citation statements)

References 23 publications

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“…Therefore, the proposed estimators are to determine the probability of the next syntax element and also to adjust the range of probability. This prediction is based on the history of the coded bins according to Equations ( 5) and (6). It always updates the range of LPS (and R LPS ) after receiving a new bin.…”

Section: Lps Updatingmentioning

confidence: 99%

“…Reviewing the standard, CABAC becomes the only entropy coding method employed by VVC, and it is the same entropy coding approach used in previous generations of video coding standards like High Efficiency Video Coding (HEVC) [3, 4] and Advanced Video Coding (AVC) [5]. However, the production stages of

\mathit {bin}

have many dependencies, making parallel processing challenging [6, 7]. To address this issue, a multiple estimators approach has been introduced to achieve entropy coding in VVC CABAC.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic estimator selection for double‐bit‐range estimation in VVC CABAC entropy coding

Im,

Chan

2024

IET Image Processing

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CABAC is the only entropy coding used in Versatile Video Coding (VVC). This is achieved through multiple estimators approach that provide more accurate predictions by considering different estimated probability results, but CABAC coding requires higher complexity and bit‐range accuracy than other approaches. Therefore, there is more potential to refine the performance from the perspective of bit allocation and architecture design. In this paper, a selection method is proposed to determine which estimator is recommended to dynamically perform the current entropy coding. Taking advantage of the double‐bit‐range architecture, the bits contained in the different estimators are also rearranged based on Most Probable Symbol () determination and Least Probable Symbol () considerations. Experimental reports in the work report that the coding time can be reduced using the proposed method and there is a slight gain in Peak Signal‐to‐Noise Ratio (PSNR) while saving some Rate‐distortion (RD) performance in bitrate.

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Section: Lps Updatingmentioning

confidence: 99%

\mathit {bin}

have many dependencies, making parallel processing challenging [6, 7]. To address this issue, a multiple estimators approach has been introduced to achieve entropy coding in VVC CABAC.…”

Section: Introductionmentioning

confidence: 99%

Dynamic estimator selection for double‐bit‐range estimation in VVC CABAC entropy coding

Im,

Chan

2024

IET Image Processing

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“…In [3,18], the BAC architecture can be configured for series of up to 15 context-coded symbols. Support for longer series is achieved by extending the adder tree with more contributions to the low register (see Figure 7).…”

Section: Optimizationsmentioning

confidence: 99%

“…Consequently, performance tends to saturate when increasing the number of symbols coded in one clock cycle [12]. In [17,18], CABAC modeling is used to obtain high-throughput rate estimations in ratedistortion optimization. However, the approximation techniques used in this study cannot be applied to bit-stream generation in BAC.…”

Section: Introductionmentioning

confidence: 99%

Optimization of the Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders

Pastuszak

2023

Electronics

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Previous studies have shown that the application of the M-coder in the H.264/AVC and H.265/HEVC video coding standards allows for highly parallel implementations without decreasing maximal frequencies. Although the primary limitation on throughput, originating from the range register update, can be eliminated, other limitations are associated with low register processing. Their negative impact is revealed at higher degrees of parallelism, leading to a gradual throughput saturation. This paper presents optimizations introduced to the generative hardware architecture to increase throughputs and hardware efficiencies. Firstly, it can process more than one bypass-mode subseries in one clock cycle. Secondly, aggregated contributions to the codestream are buffered before the low register update. Thirdly, the number of contributions used to update the low register in one clock cycle is decreased to save resources. Fourthly, the maximal one-clock-cycle renormalization shift of the low register is increased from 32 to 64 bit positions. As a result of these optimizations, the binary arithmetic coder, configured for series lengths of 27 and 2 symbols, increases the throughput from 18.37 to 37.42 symbols per clock cycle for high-quality H.265/HEVC compression. The logic consumption increases from 205.6k to 246.1k gates when synthesized on 90 nm TSMC technology. The design can operate at 570 MHz.

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“…The newly recursive block structure of motion estimation called coding tree unit (CTU), advanced motion vector prediction (AMVP), and variable prediction unit sizes. Video encoding is anticipated several consumer devices along various processing powers, 13 application‐specific video processors, 14 vector processors, 15 and these powers vary the time in battery‐powered devices as per its battery condition. Therefore, the coding complication controller is significant to act real‐time coding in various situations.…”

Section: Introductionmentioning

confidence: 99%

An efficient VLSI architecture for fast motion estimation by hybridizing parallel spiral and adaptive threshold star diamond search algorithm‐based search algorithm in HEVC

Satheeskumar,

Raghavaiah,

Geerthik

et al. 2023

Concurrency and Computation

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SummaryThis article proposes a high efficiency video coding (HEVC) standard hardware using block matching motion estimation algorithm. A hybrid parallel spiral and adaptive threshold star diamond search algorithm (Hyb PS‐ATSDSA) proposes for fast motion estimation in HEVC. Parallel spiral search approach utilizes spiral pattern for searching from center to the surroundings and adaptive threshold SDA consists of two phases, they are adaptive threshold and star diamond algorithm. To lower computational complexities in HEVC architecture, parallel spiral search algorithm uses several blocks matching schemes. Adaptive threshold and star diamond algorithm are used to reduce the matching errors and remove the invalid blocks early from the procedure of motion estimation and finally predicts the final motion of the image. Speed is increased while using this hybrid algorithm. Proposed structure is carried out in Xilinx; ISE 14.5 design suit, then the experimental outcomes are analyzed to existing motion estimation strategies in field‐programmable gate array devices. Experimental performance of the proposed Hyb‐PS‐ATSDSA‐ME‐HEVC method attains lower delay 33.97%, 32.97%, 62.97, and 26.97%, and lower area 34.867%, 45.97%, 27.97%, and 43.967% compared with the existing methods, such as FSA‐ME‐HEVC, TZSA‐ME‐HEVC, hyb TZSA‐IME‐HEVC, and IBMSA‐ME‐HEVC, respectively.

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A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC

Cited by 5 publications

References 23 publications

Dynamic estimator selection for double‐bit‐range estimation in VVC CABAC entropy coding

Dynamic estimator selection for double‐bit‐range estimation in VVC CABAC entropy coding

Optimization of the Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders

An efficient VLSI architecture for fast motion estimation by hybridizing parallel spiral and adaptive threshold star diamond search algorithm‐based search algorithm in HEVC

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