A fast and area efficient 2-D convolver for real time image processing

Yadav, Deepak; Gupta, Aditya; Mishra, Amit Kumar

doi:10.1109/tencon.2008.4766488

Cited by 5 publications

(3 citation statements)

References 8 publications

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“…In the other methods, different pipelining techniques, are exploited to increase the throughput of the proposed design. For example in [15,[19][20] the convolution is expressed as the sum-of-products among the image's pixels and the coefficients of the kernel while the ordinary pipelined convolver exploits separate pipeline stages for buffering, multiplication, and adder modules. Also, the proposed design works with high clock frequency, but it is at the expense of a huge computational overhead in each pipeline stage.…”

Section: Related Workmentioning

confidence: 99%

Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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Convolution widely has been used as the main part of the improvement in digital image processing applications. In convolutional computations, a large number of memory accesses and a huge amount of computations challenge its performance. Many of the related proposed convolvers are based on exact computations. Although exact convolvers keep the accuracy of the convolution operation at the top level, sometimes by missing a negligible amount of accuracy, the performance can be improved. Approximate computing is a new technique for solving computation overhead problems. In this paper, approximate 2D convolvers are presented which minimize the memory access rate and computations by a special factor of Multiply-and-Accumulate (MAC) terms. On the other hand, to preserve the flexibility for supporting different required accuracy, the proposed approximate convolvers are combined with the exact designs with real-time pre-processing stages by exploiting innovative methods which manage the hardware overhead. In comparison to conventional convolvers, the proposed designs improve the number of active resources which causes a significant reduction in power consumption. For 3 × 3 kernel size, the evaluation results on the Xilinx Virtex-7 (XC7V2000t) FPGA device show 34% and 20% power optimization of the proposed approximate and combined convolvers respectively, in comparison to Exact Convolver (EC). Also, this improvement grows by increasing the kernel size. Finally, a comparison based on RMSE and PSNR for different sample images and filters reveals that the error rate and image quality reduction are acceptable for many real-time image processing applications.

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Section: Related Workmentioning

confidence: 99%

Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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“…Many fast and area-efficient architectures for implementing the 2-D convolution have been proposed in the literature, with recent work focusing on implementation in FPGAs [4], [5]. Architectures based on a linear systolic array are commonplace for the fast implementation of local neighborhood functions.…”

Section: Related Workmentioning

confidence: 99%

“…It consists in individually weighting each pixel of the window and summing the weighted values, which can be expressed as follows: (5) where the are the weights. The 2-D convolution is useful to apply various types of filters to an image in order to sharpen it, blur it, enhance features such as edges, etc.…”

Section: Local Neighborhood Functionsmentioning

confidence: 99%

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Aubertin

Langlois

Savaria

2012

IEEE Trans. VLSI Syst.

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This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12 and 243 , and energy consumption reduction factors between 13 and 262.

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Neural network accelerator with fast buffer design for computer vision

Hsia,

Zhang

2024

J Real-Time Image Proc

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A fast and area efficient 2-D convolver for real time image processing

Cited by 5 publications

References 8 publications

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Neural network accelerator with fast buffer design for computer vision

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