2013 International Symposium on System on Chip (SoC) 2013
DOI: 10.1109/issoc.2013.6675277
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A family of modular area- and energy-efficient QRD-accelerator architectures

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Cited by 5 publications
(10 citation statements)
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“…A direct implementation of these operations in the hardware involves large amount of resources and higher latency. To overcome these, many methods are discussed in the literature which approximates these functions using LUT based log domain arithmetic [2,3,7], LUT based Newton-Raphson [4,5], CORDIC based architectures [9], and so forth. In [8], the square root operation is approximated using CORDIC and inverse square root is done by division.…”
Section: Background and Related Workmentioning
confidence: 99%
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“…A direct implementation of these operations in the hardware involves large amount of resources and higher latency. To overcome these, many methods are discussed in the literature which approximates these functions using LUT based log domain arithmetic [2,3,7], LUT based Newton-Raphson [4,5], CORDIC based architectures [9], and so forth. In [8], the square root operation is approximated using CORDIC and inverse square root is done by division.…”
Section: Background and Related Workmentioning
confidence: 99%
“…Implementation of the division operation and the CORDIC requires higher latency and consumes more area. In [4,5], the division operation is replaced by an LUT based Newton-Raphson method.…”
Section: Background and Related Workmentioning
confidence: 99%
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