A family of ASIC devices for next generation distributed packet switches with QoS support for IP and ATM

Abstract

The Protocol-Independent ( T ) family of ASIC devices, which we present in this paper; allows to build cost-effective IP routers and ATM switches capable of providing sophisticated Quality-of Service (QoS) guarantees in the form of throughput, delay, and jitter to individual flows or to aggregation ofjows. The new chipset, which represents the evolution of the widely used ATLANTA chipset [I], comprises jive devices. The devices presented considerable design and verijication challenges, due to the complexity and required speed of the desired QoS functionality. To solve these challenges, we devised a number of design techniques, as well as a novel ad-hoc verifkation approach.

A Scalable and Programmable Modular Traffic Manager Architecture

“…In many cases, the TM is a hard core attached to a flexible processing pipeline and represents a parameterizable TM IP core. To date, little research has been published on complete TM architectures with the only work on specific TM functions in ASIC [Chiussi et al 2001;Khan et al 2003] or FPGA [Fereydouni-Forouzandeh and Otmane 2004;IDT 2005;Krishnamurthy et al 2004]. The focus here is to derive a modular architecture that utilizes common building blocks to create the complete TM configuration.…”

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking

“…While many packetprocessing tasks can be programmed on these switches, traffic management is not one of them (more details are given in the next subsection). Programmable switches can benefit from our proposed TM by the use of externs through P4 language in its latest release P4 16 . From architectural point of view, the TM is seen like an external accelerator attached to the switch pipeline providing the necessary TM functionality and programmability needed in today's networks (More details are provided in Section III-B.6.c).…”

“…P4 16 supports integration of specialized hardware through extern. The TM is coded in C++ and can be easily ported into P4 program as an extern object/function, and attached to a flexible and programmable pipeline.…”

“…Commercially available TM solutions are either rigid because they rely on ASIC implementations, or require highspeed processing platforms [15], [19], [27]. In the research community, especially academia, only a few published works report complete TM architectures [13], [28], [29], while the majority of previous publications focus on specific functionalities such as scheduling [9], [16]- [18], and congestion management [20].…”