A dynamically configurable coprocessor for convolutional neural networks

Chakradhar, Srimat; Sankaradas, Murugan; Jakkula, Venkata; Cadambi, Srihari

doi:10.1145/1815961.1815993

Cited by 251 publications

(118 citation statements)

References 22 publications

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“…Other recent works propose different CNN acceleration hardware. For example, [3,[10][11][12]22] focus on 2D-convolvers, which play the roles of both compute modules and data caches. Meanwhile, [18,19] use FMA units for computation.…”

Section: Related Workmentioning

confidence: 99%

“…Several key similarities cause these methods to suffer from the underutilization problem we observe in our Single-CLP design. For example, the 2D-convolvers used in [3,10,12,22] must be provisioned for the largest filter across layers; they will necessarily be underutilized when computing layers with smaller filters. In [19], the organization of the compute modules depends on the number of output feature maps and their number of rows.…”

Section: Related Workmentioning

confidence: 99%

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Maximizing CNN Accelerator Efficiency Through Resource Partitioning

ShenYongming

FerdmanMichael

MilderPeter

2017

SIGARCH Comput. Archit. News

132

149

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Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based accelerators have been proposed to improve the performance and efficiency of CNNs. Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection of layers is computed. However, this approach leads to inefficient designs because the same processor structure is used to compute CNN layers of radically varying dimensions.We present a new CNN accelerator paradigm and an accompanying automated design methodology that partitions the available FPGA resources into multiple processors, each of which is tailored for a different subset of the CNN convolutional layers. Using the same FPGA resources as a single large processor, multiple smaller specialized processors increase computational efficiency and lead to a higher overall throughput. Our design methodology achieves 3.8x higher throughput than the state-of-the-art approach on evaluating the popular AlexNet CNN on a Xilinx Virtex-7 FPGA. For the more recent SqueezeNet and GoogLeNet, the speedups are 2.2x and 2.0x.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

ShenYongming

FerdmanMichael

MilderPeter

2017

SIGARCH Comput. Archit. News

132

149

View full text Add to dashboard Cite

show abstract

“…Chakradhar et al proposed mapping a CNN into a coprocessor with the dynamic reconfiguration techniques [14].…”

Section: Related Workmentioning

confidence: 99%

A Multithreaded CGRA for Convolutional Neural Network Processing

Ando¹,

Takamaeda-Yamazaki²,

Ikebe³

et al. 2017

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Convolutional neural network (CNN) is an essential model to achieve high accuracy in various machine learning applications, such as image recognition and natural language processing. One of the important issues for CNN acceleration with high energy efficiency and processing performance is efficient data reuse by exploiting the inherent data locality. In this paper, we propose a novel CGRA (Coarse Grained Reconfigurable Array) architecture with timedomain multithreading for exploiting input data locality. The multithreading on each processing element enables the input data reusing through multiple computation periods. This paper presents the accelerator design performance analysis of the proposed architecture. We examine the structure of memory subsystems, as well as the architecture of the computing array, to supply required data with minimal performance overhead. We explore efficient architecture design alternatives based on the characteristics of modern CNN configurations. The evaluation results show that the available bandwidth of the external memory can be utilized efficiently when the output plane is wider (in earlier layers of many CNNs) while the input data locality can be utilized maximally when the number of output channel is larger (in later layers).

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“…[1,2,3,4] Due to the specific computation pattern of CNN, general purpose processors hardly meet the implementation requirement, which encourages the proposal of various hardware implementations based on FPGA, GPU and ASIC [5,6,7]. CNN contains numerous 2D convolutions, which are responsible for more than 90% of the whole computation [8].…”

Section: Introductionmentioning

confidence: 99%

An efficient implementation of 2D convolution in CNN

Jing

Sha

2017

IEICE Electron. Express

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Convolutional neural network (CNN), a well-known machine learning algorithm, has been widely used in the field of computer vision for its amazing performance in image classification. With the rapid growth of applications based on CNN, various acceleration schemes have been proposed on FPGA, GPU and ASIC. In the implementation of these specific hardware accelerations, the most challenging part is the implementation of 2D convolution. To obtain a more efficient design of 2D convolution in CNN, this paper proposes a novel technique, singular value decomposition approximation (SVDA) to reduce the usage of resources. Experimental results show that the proposed SVDA hardware implementation can achieve a reduction in resources in the range of 14.46% to 37.8%, while the loss of classification accuracy is less than 1%.

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A dynamically configurable coprocessor for convolutional neural networks

Cited by 251 publications

References 22 publications

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

A Multithreaded CGRA for Convolutional Neural Network Processing

An efficient implementation of 2D convolution in CNN

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