A dynamic quality-scalable H.264 video encoder chip

Chang, Hsiu-Cheng; Yang, Yao-Chang; Chen, Jiawei; Su, Ching-Lung; Chien, Chiang‐Ju; Guo, Jiun-In; Wang, Jinn‐Shyan

doi:10.1109/aspdac.2009.4796464

Cited by 3 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The basic architecture of the proposed H.264 encoder hardware is somewhat similar to widely used architectures which adopt either three-stage or four-stage pipelined implementations [14]- [18]. Especially for the prediction of B slices in the high profile, two ME operations per MB are required for the forward and backward directions.…”

Section: B Reference Pipelined Architecturementioning

confidence: 99%

See 1 more Smart Citation

Cascaded Direction Filtering for Fast Multidirectional Inter-Prediction in H.264/AVC Main and High Profile Compression

Rhee

Kim

Lee

2012

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

Early direct mode decision is a popular technique to improve the execution speed of inter-predictions in a B slice. However, the improvement is limited when this technique is applied to a hardware-based pipelined architecture or to the video sequences where the ratio of macroblocks (MBs) encoded as the direct mode is low. This paper proposes a novel fast interprediction algorithm for B slices which increases the encoding speed by early decision of the direction of the inter-prediction using spatial and temporal correlation in a video. A speed-up is achieved by selecting a prediction direction with a lower complexity and discarding a prediction direction with a higher complexity. For the case when early mode decision is not possible, additional speed-up is achieved by partially skipping unidirectional motion estimation (ME) if the estimated cost of the ME is greater than the result of the direct mode prediction that is completed much faster than ME. This proposed sequence of early decisions is referred to as cascaded direction filtering (CDF). The proposed algorithm increases the early mode decision rate, which improves the encoding speed effectively for a hardware-based pipelined architecture as well as videos with a low ratio of MBs encoded as the direct mode. The additional memory size and bandwidth overhead required for the proposed CDF are very small. Experimental results show that the proposed CDF scheme improves the encoding speed by 45% for B slices and 32% for overall sequences. The bitrate is increased by less than 1% with a small peak signal-to-noise ratio degradation of 0.03 dB on average. Index Terms-Cascaded direction filtering, direction filtering, early direct mode decision, H.264/AVC encoder, high profile, main profile.

show abstract

Section: B Reference Pipelined Architecturementioning

confidence: 99%

“…7. Unlike a serialized architecture, the actual encoding time in pipelined architecture is improved only when the encoding times of the successive MBs are reduced by the early prediction mode decision because each stage is balanced in most pipelined architectures [14]- [18] as shown in Fig. 6.…”

Section: B Reference Pipelined Architecturementioning

confidence: 99%

Cascaded Direction Filtering for Fast Multidirectional Inter-Prediction in H.264/AVC Main and High Profile Compression

Rhee

Kim

Lee

2012

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

show abstract

“…Most of them use ASIC approach [e.g. [2][3][4][5][6], whereas the others use DSP [e.g . 7] or ASIP [e.g.…”

Section: Related Work and Problem Definitionmentioning

confidence: 99%

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip

Nguyen

Cao

Wang

et al. 2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYREMUS-II (REconfigurable MUltimedia System 2) is a coarse-grained dynamically reconfigurable computing system for multimedia and communication baseband processing. This paper proposes a real-time H.264 baseline profile encoder on REMUS-II. First, we propose an overall mapping flow for mapping algorithms onto the platform of REMUS-II system and then illustrate it by implementing the H.264 encoder. Second, parallel and pipelining techniques are considered for fully exploiting the abundant computing resources of REMUS-II, thus increasing total computing throughput and solving high computational complexity of H.264 encoder. Besides, some data-reuse schemes are also used to increase data-reuse ratio and therefore reduce the required data bandwidth. Third, we propose a scheduling scheme to manage run-time reconfiguration of the system. The scheduling is also responsible for synchronizing the data communication between tasks and handling conflict between hardware resources. Experimental results prove that the REMUS-MB (REMUS-II version for mobile applications) system can perform a real-time H.264/AVC baseline profile encoder. The encoder can encode CIF@30 fps video sequences with two reference frames and maximum search range of [−16, 15]. The implementation, thereby, can be applied to handheld devices targeted at mobile multimedia applications. The platform of REMUS-MB system is designed and synthesized by using TSMC 65 nm low power technology. The die size of REMUS-MB is 13.97 mm 2 . REMUS-MB consumes, on average, about 100 mW while working at 166 MHz. To my knowledge, in the literature this is the first implementation of H.264 encoding algorithm on a coarse-grained dynamically reconfigurable computing system.

show abstract

A survey of fast mode decision algorithms for inter-prediction and their applications to high efficiency video coding

Rhee

Lee

2012

IEEE Trans. Consumer Electron.

View full text Add to dashboard Cite

A dynamic quality-scalable H.264 video encoder chip

Cited by 3 publications

References 0 publications

Cascaded Direction Filtering for Fast Multidirectional Inter-Prediction in H.264/AVC Main and High Profile Compression

Cascaded Direction Filtering for Fast Multidirectional Inter-Prediction in H.264/AVC Main and High Profile Compression

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip

A survey of fast mode decision algorithms for inter-prediction and their applications to high efficiency video coding

Contact Info

Product

Resources

About