A dynamic quality-adjustable H.264 intra coder

Chen, Jiawei; Chang, Hsiu-Cheng; Wang, Jinn‐Shyan; Guo, Jiun-In

doi:10.1109/tce.2011.6018875

Cited by 9 publications

(8 citation statements)

References 15 publications

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“…For the high visual experience applications, our proposed design can provide 60-Hz frame rate encoding capability. However, [17] and [16], [21], [22] only process 30 frames per second for 1080-p resolution. The gate count of our design is around 258 K, with 135-MHz working frequency, implemented in 90-nm 1P9M CMOS technology.…”

Section: Implementation Resultsmentioning

confidence: 99%

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

Chen

Shen

et al. 2013

IEEE Trans. VLSI Syst.

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To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.Index Terms-All-intra, scalable video coding (SVC), VLSI architecture design.

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Section: Implementation Resultsmentioning

confidence: 99%

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

Chen

Shen

et al. 2013

IEEE Trans. VLSI Syst.

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“…Therefore, the computational demand for encoding stage is extremely high, especially in the case of real-time compression of larger video resolutions. Compared to RDO approach, SAD is the commonly used cost function for the optimal block size determination of the intra prediction in hardware architectures [1]- [3] due to its lower complexity. However, since it performs both the intra prediction algorithms simultaneously, it requires complex control and large memory capacity for their synchronization.…”

Section: Mode Decisionmentioning

confidence: 99%

An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain

Orlandić

Svarstad

2015

IEEE Trans. Consumer Electron.

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The computational complexity of the MPEG-2 to H.264/AVC transcoder, in particular the encoder, is technically challenging, but it can be reduced by reusing the information accessible in the decoding process. A low-latency mode decision algorithm performed in transform domain within the MPEG-2 decoder is proposed. The encoder stage contains two mutually exclusive intra prediction algorithms of block sizes 4x4 and 16x16 sharing the hardware logic. The shared intra prediction unit is supported by an on-chip memory organization. The proposed architecture is implemented on FPGA development board. Its implementation supports high throughputs that correspond to a real-time processing of a variety of video resolutions including QFHD 2160p at 30 fps. Furthermore, the minimal required frequency for CIF, SD and HD1080p resolutions are significantly reduced compared to the state of the art 1 . Index Terms -MPEG-2 to H.264/AVC Intra Transcoder, FPGA Hardware Implementation, DCT domain, Mode Decision.

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“…A number of hardware implementations of H.264/AVC encoders have been developed [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them [7][8][9][10][11][12][13] are dedicated only for intra coding and cannot achieve high compression efficiencies.…”

Section: Introductionmentioning

confidence: 99%

“…Some of them [7][8][9][10][11][12][13] are dedicated only for intra coding and cannot achieve high compression efficiencies. Although the remaining designs incorporate inter coding, their mode decision is taken based on SA(T)D cost measures.…”

Section: Introductionmentioning

confidence: 99%

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization

Pastuszak

2015

IEEE Trans. Circuits Syst. Video Technol.

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The rate-distortion optimization allows video encoders to achieve better compression efficiencies due to more reliable mode decisions. On the other hand, this technique involves a high computational cost when actual rates and distortions are estimated. In order to achieve real-time processing, video encoders apply simplified algorithms for mode decisions. This paper presents the H.264/AVC encoder architecture which benefits from the rate-distortion optimization and achieves high throughputs. To access actual motion vector predictors, the motion estimation is placed at the same macroblock stage as the rate-distortion mode analysis. The analysis is performed at the partition and macroblock levels. The reconstruction loop and the rate-distortion-optimization modules have the high throughput of 32 samples/coefficients per clock cycle, which enables the analysis of a significant number of preselected candidate modes. The high-throughput simplified rate estimation introduces slight quality losses and supports both entropy coding methods available in H.264/AVC. The average quality for the two coding methods is decreased by 0.07 and 0.17 dB compared to the JM17 software using the rate-distortion optimization. The compression efficiency can be traded for throughput. The architecture is verified in the real-time FPGA hardware encoder. Synthesis results show that the architecture consumes 551k gates and 148.63kB memories. It can support 1080p@60fps encoding for the 90nm TSMC technology.Index Terms-Video coding, H.264/AVC, FPGA, very largescale integration (VLSI) architecture 1051-8215 (c)

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A dynamic quality-adjustable H.264 intra coder

Cited by 9 publications

References 15 publications

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization

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