A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

Bera, L. K.; Mukherjee-Roy, Moitreyee; Abidha, B.; Agarwal, Ajay; Loh, Wei‐Yip; Tung, Chih-Hang; Kumar, R.; Trigg, A. D.; Foo, Y. L.; Tripathy, S.; Lo, G. Q.; Balasubramanian, N.; Kwong, Dim‐Lee

doi:10.1109/led.2006.872353

Cited by 7 publications

(3 citation statements)

References 12 publications

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“…Similar performance improvements can be obtained in SOI-like technologies [9,10]. In the following part, we focus on some key points of the influence of Ge content (from 0% to 60%) and strain conditions in the channel.…”

Section: Studied Devicesmentioning

confidence: 65%

“…Silicon Germanium alloys can significantly improve pMOS transistors speed as SiGe obtained by Epitaxy on Silicon exhibit an initial biaxial compressive stress known to improve hole mobility. Similar performance improvements can be obtained in SOI-like technologies [9,10]. In the following part, we focus on some key points of the influence of Ge content (from 0% to 60%) and strain conditions in the channel.…”

Section: Studied Devicesmentioning

confidence: 65%

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(Invited) In Depth Study of Ge Impact on Advanced SiGe PMOS Transistors

et al. 2014

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By using the most advanced devices, simulations and electrical characterizations as well as physicochemical tools, this paper revisit the role of SiGe layers in the improvement of performances of pMOS transistors. It is shown that an additional interfacial dipole effect due to Ge diffusion in the gate stack interfacial oxide needs to be added to the change of band structures in order to explain the dependence of threshold voltage on SiGe composition. The mobility gain brought by these alloys is then investigated. The relative role of Ge concentration, strain, interface states and strain relaxation is then discussed in detail.

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Section: Studied Devicesmentioning

confidence: 65%

Section: Studied Devicesmentioning

confidence: 65%

(Invited) In Depth Study of Ge Impact on Advanced SiGe PMOS Transistors

et al. 2014

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“…In addition, as the design rule of MOSFETs becomes below 45 nm, many reports have presented hole mobility enhancement using several compressive strained SiGe structures such as strained SiGeon-insulator, strained SiGe grown on relaxed SiGe-on-insulator, and Ge-on-insulator. This is because both electron and hole mobility enhancements are necessary in high performance CMOS by applying novel device structures (2)(3)(4)(5). We have fabricated p-MOSFETs using a compressive strained SiGe channel grown on silicon on insulator (SOI) structure to enhance the hole mobility.…”

Section: Introductionmentioning

confidence: 99%

Hole Mobility Behavior in Strained SiGe-on-SOI p-MOSFETs

Shim

Kim²,

Lee

et al. 2008

ECS Trans.

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A compressive strained SiGe channel grown-on-SOI structure which can be applicable to next generation high performance CMOSs was applied to p-MOSFETs. The mobility behavior depending on effective fields, E eff , was investigated by varying Ge concentrations in the SiGe layer. We confirmed that the mobility enhancement factor increases with both Ge concentration and E eff , and quite depends on E eff . In particular, we demonstrated that hole mobility enhancement factor at the effective fields of 0.13 MV/cm amounted to 1.51 for 34 at% Ge. In addition, we observed that the strain of 0.23 induced by 56.5-at% Ge concentration in SiGe grown-on-SOI structure could not increase hole mobility at the effective fields range from 0.05 to 0.13 MV/cm because of high density of dislocations.

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