A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory Interfaces

Lee, Jun-Yeol; Kim, Hye‐Ran; Park, Hyesung; Chun, Jung-Hoon

doi:10.1109/a-sscc48613.2020.9336112

Cited by 4 publications

(2 citation statements)

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“…Poulton et al 17 Poulton et al 18 Lee et al 20 This work This paper proposes a four-channel GRS transceiver with DC coupled equalizer. When the equilibrium value of the DC-coupled equalizer is 2.2 dB, the transceiver can transmit 25 Gb/s data over an on-package die-to-die link with a length of 6 mm and attenuation of À2.2 dB, with an energy efficiency of 1.01 pJ/bit and a BER less than 10 À12 .…”

Section: Referencementioning

confidence: 99%

“…This may have the “DC wander” issue 19 . A GRS transceiver with a 3‐tap feedforward equalizer for memory interfaces proposed in Lee et al 20 can avoid the “DC wander” issue but only operate at 10 Gb/s. None of the current systems can simultaneously cater to the demands of high‐speed die‐to‐die applications, offer high pin/energy efficiency, eliminate the drawbacks of traditional single‐ended signaling, and prevent “DC wander.”…”

Section: Introductionmentioning

confidence: 99%

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A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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Section: Referencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%