A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

Baruah, Ratul Kumar; Paily, Roy

doi:10.1109/ted.2013.2292852

Cited by 133 publications

(40 citation statements)

References 21 publications

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“…Thus, the potential distribution of novel DMG device has two abrupt changes from W1 to W2 and W2 to W3, whereas conventional DMG device has only one which is located around the middle of the gate. The abrupt change is caused by the difference of gate work function [17,30,31], and this enhances the electric field of novel and conventional DMG JLT with three and two peaks, respectively, but for SMG device, there is only one peak near the drain. The DMG DGJLT has much lower electric field peak near the drain side compared with SMG DGJLT indicating that it suppresses SCE and hot carrier effect (HCE) more effectively.…”

Section: Resultsmentioning

confidence: 99%

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang

Shan

Dou

et al. 2015

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 99%

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang

Shan

Dou

et al. 2015

Microelectronics Reliability

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“…The DMG concept has been widely studied to demonstrate the simultaneous suppression of the SCEs and enhancement of trans-conductance, due to the introduction of a step function in the channel surface potential [2][3][4][5][6][7][8][9][10][11]. Recently, improvements in electrical characteristics have been demonstrated by using the DMG structure in planar JLFETs and junctionless nanowire transistors [12,13]. In addition, the DMG structure is compatible with the current CMOS fabrication technology [14,15].…”

Section: Introductionmentioning

confidence: 99%

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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In this paper, we have developed a pseudo twodimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

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“…Furthermore as the device is scaled down to nanoscale regime high series source/drain contact resistance due to the formation of abrupt source/drain junctions become a major problem. Novel solutions such as Schottky-Barrier (metal) source/drain and Junctionless (JL) MOSFETs [8][9][10][11] have therefore been proposed and extensively investigated. The JL MOSFET possesses uniformly heavily doped source, drain and channel regions, thus having no p-n junction formation between source/drain and the channel.…”

Section: Introductionmentioning

confidence: 99%

4H-SiC-Dopant Segregated Schottky Barrier Cylindrical Gate All Around MOSFET for high speed and high power microwave applications

Kumar

Gupta

Haldar

et al. 2014

2014 IEEE 6th India International Conference on Power Electronics (IICPE)

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This paper presents extensive study of proposed 4H-Silicon Carbide (SiC) based Dopant Segregated (DS) Schottky Barrier (SB) Cylindrical Gate All Around (CGAA)MOSFET with high-k gate dielectric for hostile environment such as high temperature and radiation exposure for high power microwave applications. The Analog/RF performance of SiC-CGAA has been investigated by exploiting temperature variation from 300 K to 500 K, along with the leverage of Schottky-Barrier (SB) Source/Drain and Dopant Segregation (DS). DS is primarily used to reduce the ambipolar behavior of SB MOSFET and boost the performance of the device. Analog/RF performance in terms of main figure of merits like I on /I off , transconductance (g m ), Early Voltage, Stern Stability Factor (K), cut-off frequency (f t ) has been carried out using ATLAS-3D device simulator.

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A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

Cited by 133 publications

References 21 publications

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Improved performance of nanoscale junctionless transistor based on gate engineering approach

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

4H-SiC-Dopant Segregated Schottky Barrier Cylindrical Gate All Around MOSFET for high speed and high power microwave applications

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