Abstract:This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL 1 to WL m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read … Show more
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