A Domain-Centralized Automotive Powertrain E/E Architecture

Bandur, Victor; Pantelic, Vera; Dawson, Matthew P.; Schaap, Alexander; Wasacz, Bryon; Lawford, Mark

doi:10.4271/2021-01-0786

Cited by 11 publications

(1 citation statement)

References 18 publications

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“…However, some misconceptions still exist in some publications and reports of OEMs and Tier1 suppliers R&D center, such as zone-oriented E/E architecture topologies are considered follow-up of domainoriented E/E architecture topologies [23,[29][30][31]. Moreover, zone-oriented E/E architectures are considered equivalent to central-zonal E/E architectures, where a central vehicle computer is essential [24,36,53].…”

Section: Misconceptions and Queries On Serial Roadmapmentioning

confidence: 99%

Review of Electrical and Electronic Architectures for Autonomous Vehicles: Topologies, Networking and Simulators

Wang,

Guo,

Cao

et al. 2024

Automot. Innov.

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With the rapid development of autonomous vehicles, more and more functions and computing requirements have led to the continuous centralization in the topology of electrical and electronic (E/E) architectures. While certain Tier1 suppliers, such as BOSCH, have previously proposed a serial roadmap for E/E architecture development, implemented since 2015 with significant contributions to the automotive industry, lingering misconceptions and queries persist in actual engineering processes. Notably, there are concerns regarding the perspective of zone-oriented E/E architectures, characterized by zonal concentration, as successors to domain-oriented E/E architectures, known for functional concentration. Addressing these misconceptions and queries, this study introduces a novel parallel roadmap for E/E architecture development, concurrently evaluating domain-oriented and zone-oriented schemes. Furthermore, the study explores hybrid E/E architectures, amalgamating features from both paradigms. To align with the evolution of E/E architectures, networking technologies must adapt correspondingly. The networking mechanisms pivotal in E/E architecture design are comprehensively discussed. Additionally, the study delves into modeling and verification tools pertinent to E/E architecture topologies. In conclusion, the paper outlines existing challenges and unresolved queries in this domain.

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