A direct digital frequency synthesizer based on ROM free algorithm

Referenced Approximation Technique for a Rom-Less Sweep Frequency Synthesizer

“…This technique used a difference ∆ between two consecutive angles ( ; ) and Taylor's series of sin and cos at first order, according to the following expressions, Thus, the DDFS wave can be computed for each value of phase. However, the frequency control word should be small enough to reduce the computation error [8]. In the proposed design architecture, the quadrature DDFS comprises two registers, two adders and two multipliers [8].…”

“…However, the frequency control word should be small enough to reduce the computation error [8]. In the proposed design architecture, the quadrature DDFS comprises two registers, two adders and two multipliers [8].…”

“…For a sine curve approximation, Shu-Chnug Yi proposes to compute two simultaneous quadrature outputs [8]. This technique used a difference ∆ between two consecutive angles ( ; ) and Taylor's series of sin and cos at first order, according to the following expressions, Thus, the DDFS wave can be computed for each value of phase.…”

“…The principal methods correspond to COordinate Rotation DIgital Computer (CORDIC) algorithm, polynomial approximation as Euler infinite and chebyshev series or Taylor formulation [7], [10], [11]. An interesting work in [8], used a trigonometric approximation for small values of FCW in which the design architecture presents two advantages: low complexity (two multipliers, two adders and two registers) and one-cycle computation (no pipeline stages). However, the computation error increases strongly versus frequency control word and consequently induces a poor spurious free dynamic range.…”

“…Among these techniques, Direct Digital Frequency Synthesizers (DDFS) perform important specifications: low spurs level, fast switching speed, fast settling time, sub-hertz frequency resolution, continuous phase switching response and low phase noise [7], [8]. The principle of DDFS technique was introduced by Tierney in [9], and its corresponding conventional design architecture is shown in Figure 4, where the components are the following, -Phase accumulator: provides the time reference as counter address of the waveform memory.…”