A Digitally Assisted Multiplexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter

Abstract

This article presents a low-power (LP) area-efficient implantable neural recording system that supports high-density neural implant (HDNI) applications. The system uses a timedivision multiple access method to record from 16-neural electrodes simultaneously. A least mean squares (LMSs) algorithm is used to cancel the slowly varying electrode offsets from all channels simultaneously by using a single-tap digital adaptive filter (AF). The presented technique is fabricated in 65-nm CMOS technology and achieves a per-channel area of 0.00248 mm 2 ; 68% of which is digital circuitry (and is thus scalable with technology). The overall system consumes 3.38 µW per channel while achieving 2.6 µV rms of input referred noise (IRN) in 10 kHz of bandwidth. The proposed system has a noise efficiency factor (NEF) of 1.83 and is fully integrated on-chip.

NeuralTree: A 256-Channel 0.227-$μ$J/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC

“…This indicates that when the fine DSL is active, ∼2× noise folding occurs due to the LNA's insufficient bandwidth with respect to the ∆Σ frequency [33]. The noise performance could be improved by using a wider LNA bandwidth and lower OSR with a higher-order ∆Σ modulator [32]. Fig.…”

“…Recently, hardware sharing via time-division multiplexing has been increasingly adopted to improve the area efficiency of high-channel-count AFEs. Specifically, to cancel EDOs between successive channels, several DSL designs have been reported, including binary search [30], delta encoding [31], and least-mean-square filtering [32]. While these AFEs can ultimately settle for a fixed input EDO pattern, none are compatible with channel-selective feature extraction scheme as the offset cancellation loops must re-settle in each window when a new set of inputs (with unknown EDO patterns) is fed to the AFE.…”

Noise Power Minimization in CMOS Brain-Chip Interfaces

“…TDM operates at a frequency of f TDM = 256 kHz, given by the following equation: where f 0,neuro is the maximum frequency (1 kHz in this work) of the neuro-potential signal, N pixel = 8 is the TDM pixel count and OVR (=16) is the oversampling ratio. OVR = 16 is required to effectively sample the neural spike for the DSP stage following the a-to-d converter and N pixel = 8 is a tradeoff between the bandwidth and the number of second amplification stages in order to reduce power consumption [ 5 , 11 , 12 , 13 , 16 ]. Table 1 reports the model design parameters concerning the single channel/row analog signal processing.…”

“…In addition to that, each LNA (corresponding to each electrode) has a different voltage offset at the output node (the node connected to the input of the TDM stage) due to an electrical properties mismatch involving integrated circuits MOS transistors (MOSTs) [ 10 ]. Such offsets mainly depend on MOST threshold voltage variation and cannot be rejected by classical ac-coupling capacitors because the TDM sampling stage converts such static voltage offset into dynamic (time-domain variant) artifacts [ 11 , 12 , 13 ], whose signal power is proportional to the LNA offset voltage standard deviation.…”

Recent Trends and Future Prospects of Neural Recording Circuits and Systems: A Tutorial Brief

“…2(b) could significantly reduce the number of amplifiers and ADCs. Similar recording architectures are also explored in [7], [8]. This multiplexing technique can also be co-designed with direct digitalization converters explained in the following sections.…”