A digital signal processor for telecommunications applications

Abstract

A PROGRAMMABLE digital signal processor IC offering speed, precision, and flexibility for a variety of telecommunications applications will be discussed. Functionally, it is a specialpurpose microcomputer whose instruction set and arithmetic and addressing capabilities are optimized for realtime signal processing functions including filtering, detection and modulation. The processor can decode an instruction, fetch data and perform a 16b by 20b multiplication and a full 36b product accumulation in one machine cycle of 800ns. Signal processing functions of such applications as dual tone multifrequency receivers or low-speed data modems with a single device are thus available. The arithmetic precision of the processor is sufficient for many voicegrade applications as well. The digital signal processor can function in a stand-alone fashion in many applications requiring only an external resonator or clock. However, it easily interfaces to microprocessors and additional devices to achieve a greater degree of signal processing capability. Highly flexible and separate serial input and output ports and the ability to convert between p 255 compressed PCM and two's complement binary code formats means that the processor needs few, if any, external interface circuits even when used in complex, multiprocessor applications. 1024-word by 16b ROM for instruction and fixed coefficient storage, a 128 word by 20b RAM for variable data storage, an address arithmetic unit ( AAU) with address registers for controlling memory access, an arithmetic unit (AU) with provision for multiplication, full product accumulation, rounding and overflov protection, an 1/0 unit to control serial data transmission in and out of the circuits and a control unit which provides instruction decoding and processor synchronization. Each of these units operate in parallel and, to a large extent, independently of each other. Communication between units is accomplished by an internal 20b data bus and a 10b address bus.For program development and for some applications, external instruction and coefficient memory may be accessed over a 16b external data bus providing an alternate external address space of 1024 words. External memory access can be accomplished with no loss in processing capacity. Variable data transfers occur between the AU and either the data memory (RAM) or the I/O buffer registers. The AAU maintains an address register for the program counter and primary and auxiliary registers for coefficient read, v-ariable read and variable write data addresses. Provision also exists for single-level subroutines and program Figure 1 shows a block diagram of the circuit including a looping. Once initial addresses arc entered into the registers under program control, they are modified by the AAU as required.for signal processing functions. It performs concurrently-the primary operations of multiplication of a 16b coefficient by a 20b data word, the accumulation of a product to 40b and reduction of accumulations to 20b for data storage. The AU implements a nu...